1/*----------------------------------------
2  PERFORMANCE INSTRUMENTATION
3  Guillaume Thouvenin           08/10/98
4  David S. Miller               10/06/98
5  ---------------------------------------*/
6#ifndef PERF_COUNTER_API
7#define PERF_COUNTER_API
8
9/* sys_perfctr() interface.  First arg is operation code
10 * from enumeration below.  The meaning of further arguments
11 * are determined by the operation code.
12 *
13 * NOTE: This system call is no longer provided, use the perf_events
14 *       infrastructure.
15 *
16 * Pointers which are passed by the user are pointers to 64-bit
17 * integers.
18 *
19 * Once enabled, performance counter state is retained until the
20 * process either exits or performs an exec.  That is, performance
21 * counters remain enabled for fork/clone children.
22 */
23enum perfctr_opcode {
24	/* Enable UltraSparc performance counters, ARG0 is pointer
25	 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
26	 * to 64-bit accumulator for D1 counter.  ARG2 is a pointer to
27	 * the initial PCR register value to use.
28	 */
29	PERFCTR_ON,
30
31	/* Disable UltraSparc performance counters.  The PCR is written
32	 * with zero and the user counter accumulator pointers and
33	 * working PCR register value are forgotten.
34	 */
35	PERFCTR_OFF,
36
37	/* Add current D0 and D1 PIC values into user pointers given
38	 * in PERFCTR_ON operation.  The PIC is cleared before returning.
39	 */
40	PERFCTR_READ,
41
42	/* Clear the PIC register. */
43	PERFCTR_CLRPIC,
44
45	/* Begin using a new PCR value, the pointer to which is passed
46	 * in ARG0.  The PIC is also cleared after the new PCR value is
47	 * written.
48	 */
49	PERFCTR_SETPCR,
50
51	/* Store in pointer given in ARG0 the current PCR register value
52	 * being used.
53	 */
54	PERFCTR_GETPCR
55};
56
57#define  PRIV 0x00000001
58#define  SYS  0x00000002
59#define  USR  0x00000004
60
61/* Pic.S0 Selection Bit Field Encoding, Ultra-I/II  */
62#define  CYCLE_CNT            0x00000000
63#define  INSTR_CNT            0x00000010
64#define  DISPATCH0_IC_MISS    0x00000020
65#define  DISPATCH0_STOREBUF   0x00000030
66#define  IC_REF               0x00000080
67#define  DC_RD                0x00000090
68#define  DC_WR                0x000000A0
69#define  LOAD_USE             0x000000B0
70#define  EC_REF               0x000000C0
71#define  EC_WRITE_HIT_RDO     0x000000D0
72#define  EC_SNOOP_INV         0x000000E0
73#define  EC_RD_HIT            0x000000F0
74
75/* Pic.S0 Selection Bit Field Encoding, Ultra-III  */
76#define  US3_CYCLE_CNT	      	0x00000000
77#define  US3_INSTR_CNT	      	0x00000010
78#define  US3_DISPATCH0_IC_MISS	0x00000020
79#define  US3_DISPATCH0_BR_TGT	0x00000030
80#define  US3_DISPATCH0_2ND_BR	0x00000040
81#define  US3_RSTALL_STOREQ	0x00000050
82#define  US3_RSTALL_IU_USE	0x00000060
83#define  US3_IC_REF		0x00000080
84#define  US3_DC_RD		0x00000090
85#define  US3_DC_WR		0x000000a0
86#define  US3_EC_REF		0x000000c0
87#define  US3_EC_WR_HIT_RTO	0x000000d0
88#define  US3_EC_SNOOP_INV	0x000000e0
89#define  US3_EC_RD_MISS		0x000000f0
90#define  US3_PC_PORT0_RD	0x00000100
91#define  US3_SI_SNOOP		0x00000110
92#define  US3_SI_CIQ_FLOW	0x00000120
93#define  US3_SI_OWNED		0x00000130
94#define  US3_SW_COUNT_0		0x00000140
95#define  US3_IU_BR_MISS_TAKEN	0x00000150
96#define  US3_IU_BR_COUNT_TAKEN	0x00000160
97#define  US3_DISP_RS_MISPRED	0x00000170
98#define  US3_FA_PIPE_COMPL	0x00000180
99#define  US3_MC_READS_0		0x00000200
100#define  US3_MC_READS_1		0x00000210
101#define  US3_MC_READS_2		0x00000220
102#define  US3_MC_READS_3		0x00000230
103#define  US3_MC_STALLS_0	0x00000240
104#define  US3_MC_STALLS_2	0x00000250
105
106/* Pic.S1 Selection Bit Field Encoding, Ultra-I/II  */
107#define  CYCLE_CNT_D1         0x00000000
108#define  INSTR_CNT_D1         0x00000800
109#define  DISPATCH0_IC_MISPRED 0x00001000
110#define  DISPATCH0_FP_USE     0x00001800
111#define  IC_HIT               0x00004000
112#define  DC_RD_HIT            0x00004800
113#define  DC_WR_HIT            0x00005000
114#define  LOAD_USE_RAW         0x00005800
115#define  EC_HIT               0x00006000
116#define  EC_WB                0x00006800
117#define  EC_SNOOP_CB          0x00007000
118#define  EC_IT_HIT            0x00007800
119
120/* Pic.S1 Selection Bit Field Encoding, Ultra-III  */
121#define  US3_CYCLE_CNT_D1	0x00000000
122#define  US3_INSTR_CNT_D1	0x00000800
123#define  US3_DISPATCH0_MISPRED	0x00001000
124#define  US3_IC_MISS_CANCELLED	0x00001800
125#define  US3_RE_ENDIAN_MISS	0x00002000
126#define  US3_RE_FPU_BYPASS	0x00002800
127#define  US3_RE_DC_MISS		0x00003000
128#define  US3_RE_EC_MISS		0x00003800
129#define  US3_IC_MISS		0x00004000
130#define  US3_DC_RD_MISS		0x00004800
131#define  US3_DC_WR_MISS		0x00005000
132#define  US3_RSTALL_FP_USE	0x00005800
133#define  US3_EC_MISSES		0x00006000
134#define  US3_EC_WB		0x00006800
135#define  US3_EC_SNOOP_CB	0x00007000
136#define  US3_EC_IC_MISS		0x00007800
137#define  US3_RE_PC_MISS		0x00008000
138#define  US3_ITLB_MISS		0x00008800
139#define  US3_DTLB_MISS		0x00009000
140#define  US3_WC_MISS		0x00009800
141#define  US3_WC_SNOOP_CB	0x0000a000
142#define  US3_WC_SCRUBBED	0x0000a800
143#define  US3_WC_WB_WO_READ	0x0000b000
144#define  US3_PC_SOFT_HIT	0x0000c000
145#define  US3_PC_SNOOP_INV	0x0000c800
146#define  US3_PC_HARD_HIT	0x0000d000
147#define  US3_PC_PORT1_RD	0x0000d800
148#define  US3_SW_COUNT_1		0x0000e000
149#define  US3_IU_STAT_BR_MIS_UNTAKEN	0x0000e800
150#define  US3_IU_STAT_BR_COUNT_UNTAKEN	0x0000f000
151#define  US3_PC_MS_MISSES	0x0000f800
152#define  US3_MC_WRITES_0	0x00010800
153#define  US3_MC_WRITES_1	0x00011000
154#define  US3_MC_WRITES_2	0x00011800
155#define  US3_MC_WRITES_3	0x00012000
156#define  US3_MC_STALLS_1	0x00012800
157#define  US3_MC_STALLS_3	0x00013000
158#define  US3_RE_RAW_MISS	0x00013800
159#define  US3_FM_PIPE_COMPLETION	0x00014000
160
161struct vcounter_struct {
162  unsigned long long vcnt0;
163  unsigned long long vcnt1;
164};
165
166#endif /* !(PERF_COUNTER_API) */
167