1/*
2 * timer.h:  Definitions for the timer chips on the Sparc.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7
8#ifndef _SPARC_TIMER_H
9#define _SPARC_TIMER_H
10
11#include <linux/clocksource.h>
12#include <linux/irqreturn.h>
13
14#include <asm-generic/percpu.h>
15
16#include <asm/cpu_type.h>  /* For SUN4M_NCPUS */
17
18#define SBUS_CLOCK_RATE   2000000 /* 2MHz */
19#define TIMER_VALUE_SHIFT 9
20#define TIMER_VALUE_MASK  0x3fffff
21#define TIMER_LIMIT_BIT   (1 << 31)  /* Bit 31 in Counter-Timer register */
22
23/* The counter timer register has the value offset by 9 bits.
24 * From sun4m manual:
25 * When a counter reaches the value in the corresponding limit register,
26 * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200).
27 *
28 * To compensate for this add one to the value.
29 */
30static inline unsigned int timer_value(unsigned int value)
31{
32	return (value + 1) << TIMER_VALUE_SHIFT;
33}
34
35extern volatile u32 __iomem *master_l10_counter;
36
37irqreturn_t notrace timer_interrupt(int dummy, void *dev_id);
38
39#ifdef CONFIG_SMP
40DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent);
41void register_percpu_ce(int cpu);
42#endif
43
44#endif /* !(_SPARC_TIMER_H) */
45