1/*
2 * SH3 Setup code for SH7710, SH7712
3 *
4 *  Copyright (C) 2006 - 2009  Paul Mundt
5 *  Copyright (C) 2007  Nobuhiro Iwamatsu
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License.  See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h>
17#include <linux/sh_intc.h>
18#include <asm/rtc.h>
19
20enum {
21	UNUSED = 0,
22
23	/* interrupt sources */
24	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
25	DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
26	EDMAC0, EDMAC1, EDMAC2,
27	SIOF0, SIOF1,
28
29	TMU0, TMU1, TMU2,
30	RTC, WDT, REF,
31};
32
33static struct intc_vect vectors[] __initdata = {
34	/* IRQ0->5 are handled in setup-sh3.c */
35	INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
36	INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
37	INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
38	INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
39	INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
40	INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
41	INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
42#ifdef CONFIG_CPU_SUBTYPE_SH7710
43	INTC_VECT(IPSEC, 0xbe0),
44#endif
45	INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
46	INTC_VECT(EDMAC2, 0xc40),
47	INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
48	INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
49	INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
50	INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
51	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
52	INTC_VECT(TMU2, 0x440),
53	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
54	INTC_VECT(RTC, 0x4c0),
55	INTC_VECT(WDT, 0x560),
56	INTC_VECT(REF, 0x580),
57};
58
59static struct intc_prio_reg prio_registers[] __initdata = {
60	{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
61	{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
62	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
63	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
64	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
65	{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
66	{ 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
67	{ 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
68	{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
69};
70
71static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
72			 NULL, prio_registers, NULL);
73
74static struct resource rtc_resources[] = {
75	[0] =	{
76		.start	= 0xa413fec0,
77		.end	= 0xa413fec0 + 0x1e,
78		.flags  = IORESOURCE_IO,
79	},
80	[1] =	{
81		.start  = evt2irq(0x480),
82		.flags	= IORESOURCE_IRQ,
83	},
84};
85
86static struct sh_rtc_platform_info rtc_info = {
87	.capabilities	= RTC_CAP_4_DIGIT_YEAR,
88};
89
90static struct platform_device rtc_device = {
91	.name		= "sh-rtc",
92	.id		= -1,
93	.num_resources	= ARRAY_SIZE(rtc_resources),
94	.resource	= rtc_resources,
95	.dev		= {
96		.platform_data = &rtc_info,
97	},
98};
99
100static struct plat_sci_port scif0_platform_data = {
101	.flags		= UPF_BOOT_AUTOCONF,
102	.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE |
103			  SCSCR_CKE1 | SCSCR_CKE0,
104	.type		= PORT_SCIF,
105};
106
107static struct resource scif0_resources[] = {
108	DEFINE_RES_MEM(0xa4400000, 0x100),
109	DEFINE_RES_IRQ(evt2irq(0x880)),
110};
111
112static struct platform_device scif0_device = {
113	.name		= "sh-sci",
114	.id		= 0,
115	.resource	= scif0_resources,
116	.num_resources	= ARRAY_SIZE(scif0_resources),
117	.dev		= {
118		.platform_data	= &scif0_platform_data,
119	},
120};
121
122static struct plat_sci_port scif1_platform_data = {
123	.flags		= UPF_BOOT_AUTOCONF,
124	.scscr		= SCSCR_TE | SCSCR_RE | SCSCR_REIE |
125			  SCSCR_CKE1 | SCSCR_CKE0,
126	.type		= PORT_SCIF,
127};
128
129static struct resource scif1_resources[] = {
130	DEFINE_RES_MEM(0xa4410000, 0x100),
131	DEFINE_RES_IRQ(evt2irq(0x900)),
132};
133
134static struct platform_device scif1_device = {
135	.name		= "sh-sci",
136	.id		= 1,
137	.resource	= scif1_resources,
138	.num_resources	= ARRAY_SIZE(scif1_resources),
139	.dev		= {
140		.platform_data	= &scif1_platform_data,
141	},
142};
143
144static struct sh_timer_config tmu0_platform_data = {
145	.channels_mask = 7,
146};
147
148static struct resource tmu0_resources[] = {
149	DEFINE_RES_MEM(0xa412fe90, 0x28),
150	DEFINE_RES_IRQ(evt2irq(0x400)),
151	DEFINE_RES_IRQ(evt2irq(0x420)),
152	DEFINE_RES_IRQ(evt2irq(0x440)),
153};
154
155static struct platform_device tmu0_device = {
156	.name		= "sh-tmu-sh3",
157	.id		= 0,
158	.dev = {
159		.platform_data	= &tmu0_platform_data,
160	},
161	.resource	= tmu0_resources,
162	.num_resources	= ARRAY_SIZE(tmu0_resources),
163};
164
165static struct platform_device *sh7710_devices[] __initdata = {
166	&scif0_device,
167	&scif1_device,
168	&tmu0_device,
169	&rtc_device,
170};
171
172static int __init sh7710_devices_setup(void)
173{
174	return platform_add_devices(sh7710_devices,
175				    ARRAY_SIZE(sh7710_devices));
176}
177arch_initcall(sh7710_devices_setup);
178
179static struct platform_device *sh7710_early_devices[] __initdata = {
180	&scif0_device,
181	&scif1_device,
182	&tmu0_device,
183};
184
185void __init plat_early_device_setup(void)
186{
187	early_platform_add_devices(sh7710_early_devices,
188				   ARRAY_SIZE(sh7710_early_devices));
189}
190
191void __init plat_irq_setup(void)
192{
193	register_intc_controller(&intc_desc);
194	plat_irq_setup_sh3();
195}
196