1#include <asm/reg.h>
2#include <asm/ppc_asm.h>
3#include <asm/processor.h>
4
5
6.text
7
8_GLOBAL(mpc52xx_deep_sleep)
9mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
10
11	/* enable interrupts */
12	mfmsr	r7
13	ori	r7, r7, 0x8000 /* EE */
14	mtmsr	r7
15	sync; isync;
16
17	li	r10, 0 /* flag that irq handler sets */
18
19	/* enable tmr7 (or any other) interrupt */
20	lwz	r8, 0x14(r6) /* intr->main_mask */
21	ori	r8, r8, 0x1
22	xori	r8, r8, 0x1
23	stw	r8, 0x14(r6)
24	sync
25
26	/* emulate tmr7 interrupt */
27	li	r8, 0x1
28	stw	r8, 0x40(r6) /* intr->main_emulate */
29	sync
30
31	/* wait for it to happen */
321:
33	cmpi	cr0, r10, 1
34	bne	cr0, 1b
35
36	/* lock icache */
37	mfspr	r10, SPRN_HID0
38	ori	r10, r10, 0x2000
39	sync; isync;
40	mtspr	SPRN_HID0, r10
41	sync; isync;
42
43
44	mflr	r9 /* save LR */
45
46	/* jump to sram */
47	mtlr	r3
48	blrl
49
50	mtlr	r9 /* restore LR */
51
52	/* unlock icache */
53	mfspr	r10, SPRN_HID0
54	ori	r10, r10, 0x2000
55	xori	r10, r10, 0x2000
56	sync; isync;
57	mtspr	SPRN_HID0, r10
58	sync; isync;
59
60
61	/* return to C code */
62	blr
63
64
65_GLOBAL(mpc52xx_ds_sram)
66mpc52xx_ds_sram:
67	/* put SDRAM into self-refresh */
68	lwz	r8, 0x4(r4)	/* sdram->ctrl */
69
70	oris	r8, r8, 0x8000 /* mode_en */
71	stw	r8, 0x4(r4)
72	sync
73
74	ori	r8, r8, 0x0002 /* soft_pre */
75	stw	r8, 0x4(r4)
76	sync
77	xori	r8, r8, 0x0002
78
79	xoris	r8, r8, 0x8000 /* !mode_en */
80	stw	r8, 0x4(r4)
81	sync
82
83	oris	r8, r8, 0x5000
84	xoris	r8, r8, 0x4000 /* ref_en !cke */
85	stw	r8, 0x4(r4)
86	sync
87
88	/* disable SDRAM clock */
89	lwz	r8, 0x14(r5) /* cdm->clkenable */
90	ori	r8, r8, 0x0008
91	xori	r8, r8, 0x0008
92	stw	r8, 0x14(r5)
93	sync
94
95
96	/* put mpc5200 to sleep */
97	mfmsr	r10
98	oris	r10, r10, 0x0004	/* POW = 1 */
99	sync; isync;
100	mtmsr	r10
101	sync; isync;
102
103
104	/* enable clock */
105	lwz	r8, 0x14(r5)
106	ori	r8, r8, 0x0008
107	stw	r8, 0x14(r5)
108	sync
109
110	/* get ram out of self-refresh */
111	lwz	r8, 0x4(r4)
112	oris	r8, r8, 0x5000 /* cke ref_en */
113	stw	r8, 0x4(r4)
114	sync
115
116	blr
117_GLOBAL(mpc52xx_ds_sram_size)
118mpc52xx_ds_sram_size:
119	.long $-mpc52xx_ds_sram
120
121
122/* ### interrupt handler for wakeup from deep-sleep ### */
123_GLOBAL(mpc52xx_ds_cached)
124mpc52xx_ds_cached:
125	mtspr	SPRN_SPRG0, r7
126	mtspr	SPRN_SPRG1, r8
127
128	/* disable emulated interrupt */
129	mfspr	r7, 311 /* MBAR */
130	addi	r7, r7, 0x540	/* intr->main_emul */
131	li	r8, 0
132	stw	r8, 0(r7)
133	sync
134	dcbf	0, r7
135
136	/* acknowledge wakeup, so CCS releases power pown */
137	mfspr	r7, 311	/* MBAR */
138	addi	r7, r7, 0x524	/* intr->enc_status */
139	lwz	r8, 0(r7)
140	ori	r8, r8, 0x0400
141	stw	r8, 0(r7)
142	sync
143	dcbf	0, r7
144
145	/* flag - we handled the interrupt */
146	li	r10, 1
147
148	mfspr	r8, SPRN_SPRG1
149	mfspr	r7, SPRN_SPRG0
150
151	rfi
152_GLOBAL(mpc52xx_ds_cached_size)
153mpc52xx_ds_cached_size:
154	.long $-mpc52xx_ds_cached
155