1/* 2 * Definitions for using the Apple Descriptor-Based DMA controller 3 * in Power Macintosh computers. 4 * 5 * Copyright (C) 1996 Paul Mackerras. 6 */ 7 8#ifdef __KERNEL__ 9#ifndef _ASM_DBDMA_H_ 10#define _ASM_DBDMA_H_ 11/* 12 * DBDMA control/status registers. All little-endian. 13 */ 14struct dbdma_regs { 15 unsigned int control; /* lets you change bits in status */ 16 unsigned int status; /* DMA and device status bits (see below) */ 17 unsigned int cmdptr_hi; /* upper 32 bits of command address */ 18 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */ 19 unsigned int intr_sel; /* select interrupt condition bit */ 20 unsigned int br_sel; /* select branch condition bit */ 21 unsigned int wait_sel; /* select wait condition bit */ 22 unsigned int xfer_mode; 23 unsigned int data2ptr_hi; 24 unsigned int data2ptr; 25 unsigned int res1; 26 unsigned int address_hi; 27 unsigned int br_addr_hi; 28 unsigned int res2[3]; 29}; 30 31/* Bits in control and status registers */ 32#define RUN 0x8000 33#define PAUSE 0x4000 34#define FLUSH 0x2000 35#define WAKE 0x1000 36#define DEAD 0x0800 37#define ACTIVE 0x0400 38#define BT 0x0100 39#define DEVSTAT 0x00ff 40 41/* 42 * DBDMA command structure. These fields are all little-endian! 43 */ 44struct dbdma_cmd { 45 __le16 req_count; /* requested byte transfer count */ 46 __le16 command; /* command word (has bit-fields) */ 47 __le32 phy_addr; /* physical data address */ 48 __le32 cmd_dep; /* command-dependent field */ 49 __le16 res_count; /* residual count after completion */ 50 __le16 xfer_status; /* transfer status */ 51}; 52 53/* DBDMA command values in command field */ 54#define OUTPUT_MORE 0 /* transfer memory data to stream */ 55#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ 56#define INPUT_MORE 0x2000 /* transfer stream data to memory */ 57#define INPUT_LAST 0x3000 /* ditto, expect end marker */ 58#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ 59#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ 60#define DBDMA_NOP 0x6000 /* do nothing */ 61#define DBDMA_STOP 0x7000 /* suspend processing */ 62 63/* Key values in command field */ 64#define KEY_STREAM0 0 /* usual data stream */ 65#define KEY_STREAM1 0x100 /* control/status stream */ 66#define KEY_STREAM2 0x200 /* device-dependent stream */ 67#define KEY_STREAM3 0x300 /* device-dependent stream */ 68#define KEY_REGS 0x500 /* device register space */ 69#define KEY_SYSTEM 0x600 /* system memory-mapped space */ 70#define KEY_DEVICE 0x700 /* device memory-mapped space */ 71 72/* Interrupt control values in command field */ 73#define INTR_NEVER 0 /* don't interrupt */ 74#define INTR_IFSET 0x10 /* intr if condition bit is 1 */ 75#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */ 76#define INTR_ALWAYS 0x30 /* always interrupt */ 77 78/* Branch control values in command field */ 79#define BR_NEVER 0 /* don't branch */ 80#define BR_IFSET 0x4 /* branch if condition bit is 1 */ 81#define BR_IFCLR 0x8 /* branch if condition bit is 0 */ 82#define BR_ALWAYS 0xc /* always branch */ 83 84/* Wait control values in command field */ 85#define WAIT_NEVER 0 /* don't wait */ 86#define WAIT_IFSET 1 /* wait if condition bit is 1 */ 87#define WAIT_IFCLR 2 /* wait if condition bit is 0 */ 88#define WAIT_ALWAYS 3 /* always wait */ 89 90/* Align an address for a DBDMA command structure */ 91#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \ 92 & -sizeof(struct dbdma_cmd)) 93 94/* Useful macros */ 95#define DBDMA_DO_STOP(regs) do { \ 96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ 97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \ 98 ; \ 99} while(0) 100 101#define DBDMA_DO_RESET(regs) do { \ 102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\ 103 while(in_le32(&((regs)->status)) & (RUN)) \ 104 ; \ 105} while(0) 106 107#endif /* _ASM_DBDMA_H_ */ 108#endif /* __KERNEL__ */ 109