1#include <linux/kernel.h>
2#include <linux/pci.h>
3#include <asm/bootinfo.h>
4
5#include <asm/lasat/lasat.h>
6#include <asm/nile4.h>
7
8#define PCI_ACCESS_READ	 0
9#define PCI_ACCESS_WRITE 1
10
11#define LO(reg) (reg / 4)
12#define HI(reg) (reg / 4 + 1)
13
14volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
15
16static int nile4_pcibios_config_access(unsigned char access_type,
17	struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
18{
19	unsigned char busnum = bus->number;
20	u32 adr, mask, err;
21
22	if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
23		/* The addressing scheme chosen leaves room for just
24		 * 8 devices on the first busnum (besides the PCI
25		 * controller itself) */
26		return PCIBIOS_DEVICE_NOT_FOUND;
27
28	if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
29		/* Access controller registers directly */
30		if (access_type == PCI_ACCESS_WRITE) {
31			vrc_pciregs[(0x200 + where) >> 2] = *val;
32		} else {
33			*val = vrc_pciregs[(0x200 + where) >> 2];
34		}
35		return PCIBIOS_SUCCESSFUL;
36	}
37
38	/* Temporarily map PCI Window 1 to config space */
39	mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
40	vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
41
42	/* Clear PCI Error register. This also clears the Error Type
43	 * bits in the Control register */
44	vrc_pciregs[LO(NILE4_PCIERR)] = 0;
45	vrc_pciregs[HI(NILE4_PCIERR)] = 0;
46
47	/* Setup address */
48	if (busnum == 0)
49		adr =
50		    KSEG1ADDR(PCI_WINDOW1) +
51		    ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
52		     | (where & ~3));
53	else
54		adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
55		      (where & ~3);
56
57	if (access_type == PCI_ACCESS_WRITE)
58		*(u32 *) adr = *val;
59	else
60		*val = *(u32 *) adr;
61
62	/* Check for master or target abort */
63	err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
64
65	/* Restore PCI Window 1 */
66	vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
67
68	if (err)
69		return PCIBIOS_DEVICE_NOT_FOUND;
70
71	return PCIBIOS_SUCCESSFUL;
72}
73
74static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
75	int where, int size, u32 *val)
76{
77	u32 data = 0;
78	int err;
79
80	if ((size == 2) && (where & 1))
81		return PCIBIOS_BAD_REGISTER_NUMBER;
82	else if ((size == 4) && (where & 3))
83		return PCIBIOS_BAD_REGISTER_NUMBER;
84
85	err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
86					  &data);
87	if (err)
88		return err;
89
90	if (size == 1)
91		*val = (data >> ((where & 3) << 3)) & 0xff;
92	else if (size == 2)
93		*val = (data >> ((where & 3) << 3)) & 0xffff;
94	else
95		*val = data;
96
97	return PCIBIOS_SUCCESSFUL;
98}
99
100static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
101	int where, int size, u32 val)
102{
103	u32 data = 0;
104	int err;
105
106	if ((size == 2) && (where & 1))
107		return PCIBIOS_BAD_REGISTER_NUMBER;
108	else if ((size == 4) && (where & 3))
109		return PCIBIOS_BAD_REGISTER_NUMBER;
110
111	err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
112					  &data);
113	if (err)
114		return err;
115
116	if (size == 1)
117		data = (data & ~(0xff << ((where & 3) << 3))) |
118		    (val << ((where & 3) << 3));
119	else if (size == 2)
120		data = (data & ~(0xffff << ((where & 3) << 3))) |
121		    (val << ((where & 3) << 3));
122	else
123		data = val;
124
125	if (nile4_pcibios_config_access
126	    (PCI_ACCESS_WRITE, bus, devfn, where, &data))
127		return -1;
128
129	return PCIBIOS_SUCCESSFUL;
130}
131
132struct pci_ops nile4_pci_ops = {
133	.read = nile4_pcibios_read,
134	.write = nile4_pcibios_write,
135};
136