1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * PROM library initialisation code. 7 * 8 * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. 9 * All rights reserved. 10 * Authors: Carsten Langgaard <carstenl@mips.com> 11 * Maciej W. Rozycki <macro@mips.com> 12 * Steven J. Hill <sjhill@mips.com> 13 */ 14#include <linux/init.h> 15#include <linux/string.h> 16#include <linux/kernel.h> 17#include <linux/serial_core.h> 18 19#include <asm/cacheflush.h> 20#include <asm/smp-ops.h> 21#include <asm/traps.h> 22#include <asm/fw/fw.h> 23#include <asm/mips-cm.h> 24#include <asm/mips-cpc.h> 25#include <asm/mips-boards/generic.h> 26#include <asm/mips-boards/malta.h> 27 28static int mips_revision_corid; 29int mips_revision_sconid; 30 31/* Bonito64 system controller register base. */ 32unsigned long _pcictrl_bonito; 33unsigned long _pcictrl_bonito_pcicfg; 34 35/* GT64120 system controller register base */ 36unsigned long _pcictrl_gt64120; 37 38/* MIPS System controller register base */ 39unsigned long _pcictrl_msc; 40 41#ifdef CONFIG_SERIAL_8250_CONSOLE 42static void __init console_config(void) 43{ 44 char console_string[40]; 45 int baud = 0; 46 char parity = '\0', bits = '\0', flow = '\0'; 47 char *s; 48 49 s = fw_getenv("modetty0"); 50 if (s) { 51 while (*s >= '0' && *s <= '9') 52 baud = baud*10 + *s++ - '0'; 53 if (*s == ',') 54 s++; 55 if (*s) 56 parity = *s++; 57 if (*s == ',') 58 s++; 59 if (*s) 60 bits = *s++; 61 if (*s == ',') 62 s++; 63 if (*s == 'h') 64 flow = 'r'; 65 } 66 if (baud == 0) 67 baud = 38400; 68 if (parity != 'n' && parity != 'o' && parity != 'e') 69 parity = 'n'; 70 if (bits != '7' && bits != '8') 71 bits = '8'; 72 if (flow == '\0') 73 flow = 'r'; 74 75 if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) { 76 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, 77 parity, bits); 78 setup_earlycon(console_string); 79 } 80 81 if ((strstr(fw_getcmdline(), "console=")) == NULL) { 82 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 83 parity, bits, flow); 84 strcat(fw_getcmdline(), console_string); 85 pr_info("Config serial console:%s\n", console_string); 86 } 87} 88#endif 89 90static void __init mips_nmi_setup(void) 91{ 92 void *base; 93 extern char except_vec_nmi; 94 95 base = cpu_has_veic ? 96 (void *)(CAC_BASE + 0xa80) : 97 (void *)(CAC_BASE + 0x380); 98 memcpy(base, &except_vec_nmi, 0x80); 99 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 100} 101 102static void __init mips_ejtag_setup(void) 103{ 104 void *base; 105 extern char except_vec_ejtag_debug; 106 107 base = cpu_has_veic ? 108 (void *)(CAC_BASE + 0xa00) : 109 (void *)(CAC_BASE + 0x300); 110 memcpy(base, &except_vec_ejtag_debug, 0x80); 111 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 112} 113 114phys_addr_t mips_cpc_default_phys_base(void) 115{ 116 return CPC_BASE_ADDR; 117} 118 119void __init prom_init(void) 120{ 121 mips_display_message("LINUX"); 122 123 /* 124 * early setup of _pcictrl_bonito so that we can determine 125 * the system controller on a CORE_EMUL board 126 */ 127 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); 128 129 mips_revision_corid = MIPS_REVISION_CORID; 130 131 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 132 if (BONITO_PCIDID == 0x0001df53 || 133 BONITO_PCIDID == 0x0003df53) 134 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 135 else 136 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; 137 } 138 139 mips_revision_sconid = MIPS_REVISION_SCONID; 140 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { 141 switch (mips_revision_corid) { 142 case MIPS_REVISION_CORID_QED_RM5261: 143 case MIPS_REVISION_CORID_CORE_LV: 144 case MIPS_REVISION_CORID_CORE_FPGA: 145 case MIPS_REVISION_CORID_CORE_FPGAR2: 146 mips_revision_sconid = MIPS_REVISION_SCON_GT64120; 147 break; 148 case MIPS_REVISION_CORID_CORE_EMUL_BON: 149 case MIPS_REVISION_CORID_BONITO64: 150 case MIPS_REVISION_CORID_CORE_20K: 151 mips_revision_sconid = MIPS_REVISION_SCON_BONITO; 152 break; 153 case MIPS_REVISION_CORID_CORE_MSC: 154 case MIPS_REVISION_CORID_CORE_FPGA2: 155 case MIPS_REVISION_CORID_CORE_24K: 156 /* 157 * SOCit/ROCit support is essentially identical 158 * but make an attempt to distinguish them 159 */ 160 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; 161 break; 162 case MIPS_REVISION_CORID_CORE_FPGA3: 163 case MIPS_REVISION_CORID_CORE_FPGA4: 164 case MIPS_REVISION_CORID_CORE_FPGA5: 165 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 166 default: 167 /* See above */ 168 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; 169 break; 170 } 171 } 172 173 switch (mips_revision_sconid) { 174 u32 start, map, mask, data; 175 176 case MIPS_REVISION_SCON_GT64120: 177 /* 178 * Setup the North bridge to do Master byte-lane swapping 179 * when running in bigendian. 180 */ 181 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); 182 183#ifdef CONFIG_CPU_LITTLE_ENDIAN 184 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | 185 GT_PCI0_CMD_SBYTESWAP_BIT); 186#else 187 GT_WRITE(GT_PCI0_CMD_OFS, 0); 188#endif 189 /* Fix up PCI I/O mapping if necessary (for Atlas). */ 190 start = GT_READ(GT_PCI0IOLD_OFS); 191 map = GT_READ(GT_PCI0IOREMAP_OFS); 192 if ((start & map) != 0) { 193 map &= ~start; 194 GT_WRITE(GT_PCI0IOREMAP_OFS, map); 195 } 196 197 set_io_port_base(MALTA_GT_PORT_BASE); 198 break; 199 200 case MIPS_REVISION_SCON_BONITO: 201 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); 202 203 /* 204 * Disable Bonito IOBC. 205 */ 206 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 207 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 208 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 209 210 /* 211 * Setup the North bridge to do Master byte-lane swapping 212 * when running in bigendian. 213 */ 214#ifdef CONFIG_CPU_LITTLE_ENDIAN 215 BONITO_BONGENCFG = BONITO_BONGENCFG & 216 ~(BONITO_BONGENCFG_MSTRBYTESWAP | 217 BONITO_BONGENCFG_BYTESWAP); 218#else 219 BONITO_BONGENCFG = BONITO_BONGENCFG | 220 BONITO_BONGENCFG_MSTRBYTESWAP | 221 BONITO_BONGENCFG_BYTESWAP; 222#endif 223 224 set_io_port_base(MALTA_BONITO_PORT_BASE); 225 break; 226 227 case MIPS_REVISION_SCON_SOCIT: 228 case MIPS_REVISION_SCON_ROCIT: 229 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 230mips_pci_controller: 231 mb(); 232 MSC_READ(MSC01_PCI_CFG, data); 233 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); 234 wmb(); 235 236 /* Fix up lane swapping. */ 237#ifdef CONFIG_CPU_LITTLE_ENDIAN 238 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 239#else 240 MSC_WRITE(MSC01_PCI_SWAP, 241 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | 242 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | 243 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); 244#endif 245#ifndef CONFIG_EVA 246 /* Fix up target memory mapping. */ 247 MSC_READ(MSC01_PCI_BAR0, mask); 248 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); 249#else 250 /* 251 * Setup the Malta max (2GB) memory for PCI DMA in host bridge 252 * in transparent addressing mode, starting from 0x80000000. 253 */ 254 mask = PHYS_OFFSET | (1<<3); 255 MSC_WRITE(MSC01_PCI_BAR0, mask); 256 257 mask = PHYS_OFFSET; 258 MSC_WRITE(MSC01_PCI_HEAD4, mask); 259 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask); 260 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask); 261#endif 262 /* Don't handle target retries indefinitely. */ 263 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == 264 MSC01_PCI_CFG_MAXRTRY_MSK) 265 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << 266 MSC01_PCI_CFG_MAXRTRY_SHF)) | 267 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << 268 MSC01_PCI_CFG_MAXRTRY_SHF); 269 270 wmb(); 271 MSC_WRITE(MSC01_PCI_CFG, data); 272 mb(); 273 274 set_io_port_base(MALTA_MSC_PORT_BASE); 275 break; 276 277 case MIPS_REVISION_SCON_SOCITSC: 278 case MIPS_REVISION_SCON_SOCITSCP: 279 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); 280 goto mips_pci_controller; 281 282 default: 283 /* Unknown system controller */ 284 mips_display_message("SC Error"); 285 while (1); /* We die here... */ 286 } 287 board_nmi_handler_setup = mips_nmi_setup; 288 board_ejtag_handler_setup = mips_ejtag_setup; 289 290 fw_init_cmdline(); 291 fw_meminit(); 292#ifdef CONFIG_SERIAL_8250_CONSOLE 293 console_config(); 294#endif 295 /* Early detection of CMP support */ 296 mips_cm_probe(); 297 mips_cpc_probe(); 298 299 if (!register_cps_smp_ops()) 300 return; 301 if (!register_cmp_smp_ops()) 302 return; 303 if (!register_vsmp_smp_ops()) 304 return; 305 register_up_smp_ops(); 306} 307 308void platform_early_l2_init(void) 309{ 310 /* L2 configuration lives in the CM3 */ 311 if (mips_cm_revision() >= CM_REV_CM3) 312 mips_cm_probe(); 313} 314