1/*
2 * This program is free software; you can redistribute	it and/or modify it
3 * under  the terms of	the GNU General	 Public License as published by the
4 * Free Software Foundation;  either version 2 of the  License, or (at your
5 * option) any later version.
6 *
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
9 *
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
11 */
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/kernel_stat.h>
16#include <asm/io.h>
17#include <asm/irq.h>
18#include <asm/msc01_ic.h>
19#include <asm/traps.h>
20
21static unsigned long _icctrl_msc;
22#define MSC01_IC_REG_BASE	_icctrl_msc
23
24#define MSCIC_WRITE(reg, data)	do { *(volatile u32 *)(reg) = data; } while (0)
25#define MSCIC_READ(reg, data)	do { data = *(volatile u32 *)(reg); } while (0)
26
27static unsigned int irq_base;
28
29/* mask off an interrupt */
30static inline void mask_msc_irq(struct irq_data *d)
31{
32	unsigned int irq = d->irq;
33
34	if (irq < (irq_base + 32))
35		MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
36	else
37		MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
38}
39
40/* unmask an interrupt */
41static inline void unmask_msc_irq(struct irq_data *d)
42{
43	unsigned int irq = d->irq;
44
45	if (irq < (irq_base + 32))
46		MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
47	else
48		MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
49}
50
51/*
52 * Masks and ACKs an IRQ
53 */
54static void level_mask_and_ack_msc_irq(struct irq_data *d)
55{
56	mask_msc_irq(d);
57	if (!cpu_has_veic)
58		MSCIC_WRITE(MSC01_IC_EOI, 0);
59}
60
61/*
62 * Masks and ACKs an IRQ
63 */
64static void edge_mask_and_ack_msc_irq(struct irq_data *d)
65{
66	unsigned int irq = d->irq;
67
68	mask_msc_irq(d);
69	if (!cpu_has_veic)
70		MSCIC_WRITE(MSC01_IC_EOI, 0);
71	else {
72		u32 r;
73		MSCIC_READ(MSC01_IC_SUP+irq*8, r);
74		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
75		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
76	}
77}
78
79/*
80 * Interrupt handler for interrupts coming from SOC-it.
81 */
82void ll_msc_irq(void)
83{
84	unsigned int irq;
85
86	/* read the interrupt vector register */
87	MSCIC_READ(MSC01_IC_VEC, irq);
88	if (irq < 64)
89		do_IRQ(irq + irq_base);
90	else {
91		/* Ignore spurious interrupt */
92	}
93}
94
95static void msc_bind_eic_interrupt(int irq, int set)
96{
97	MSCIC_WRITE(MSC01_IC_RAMW,
98		    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
99}
100
101static struct irq_chip msc_levelirq_type = {
102	.name = "SOC-it-Level",
103	.irq_ack = level_mask_and_ack_msc_irq,
104	.irq_mask = mask_msc_irq,
105	.irq_mask_ack = level_mask_and_ack_msc_irq,
106	.irq_unmask = unmask_msc_irq,
107	.irq_eoi = unmask_msc_irq,
108};
109
110static struct irq_chip msc_edgeirq_type = {
111	.name = "SOC-it-Edge",
112	.irq_ack = edge_mask_and_ack_msc_irq,
113	.irq_mask = mask_msc_irq,
114	.irq_mask_ack = edge_mask_and_ack_msc_irq,
115	.irq_unmask = unmask_msc_irq,
116	.irq_eoi = unmask_msc_irq,
117};
118
119
120void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
121{
122	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
123
124	/* Reset interrupt controller - initialises all registers to 0 */
125	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
126
127	board_bind_eic_interrupt = &msc_bind_eic_interrupt;
128
129	for (; nirq > 0; nirq--, imp++) {
130		int n = imp->im_irq;
131
132		switch (imp->im_type) {
133		case MSC01_IRQ_EDGE:
134			irq_set_chip_and_handler_name(irqbase + n,
135						      &msc_edgeirq_type,
136						      handle_edge_irq,
137						      "edge");
138			if (cpu_has_veic)
139				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
140			else
141				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
142			break;
143		case MSC01_IRQ_LEVEL:
144			irq_set_chip_and_handler_name(irqbase + n,
145						      &msc_levelirq_type,
146						      handle_level_irq,
147						      "level");
148			if (cpu_has_veic)
149				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
150			else
151				MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
152		}
153	}
154
155	irq_base = irqbase;
156
157	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */
158
159}
160