1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17 */
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/percpu.h>
22#include <linux/smp.h>
23
24#include <asm/addrspace.h>
25#include <asm/io.h>
26#include <asm/time.h>
27
28#include <asm/sibyte/sb1250.h>
29#include <asm/sibyte/sb1250_regs.h>
30#include <asm/sibyte/sb1250_int.h>
31#include <asm/sibyte/sb1250_scd.h>
32
33#define IMR_IP2_VAL	K_INT_MAP_I0
34#define IMR_IP3_VAL	K_INT_MAP_I1
35#define IMR_IP4_VAL	K_INT_MAP_I2
36
37/*
38 * The general purpose timer ticks at 1MHz independent if
39 * the rest of the system
40 */
41
42static int sibyte_shutdown(struct clock_event_device *evt)
43{
44	void __iomem *cfg;
45
46	cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG));
47
48	/* Stop the timer until we actually program a shot */
49	__raw_writeq(0, cfg);
50
51	return 0;
52}
53
54static int sibyte_set_periodic(struct clock_event_device *evt)
55{
56	unsigned int cpu = smp_processor_id();
57	void __iomem *cfg, *init;
58
59	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
60	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
61
62	__raw_writeq(0, cfg);
63	__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
64	__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
65
66	return 0;
67}
68
69static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
70{
71	unsigned int cpu = smp_processor_id();
72	void __iomem *cfg, *init;
73
74	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
75	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
76
77	__raw_writeq(0, cfg);
78	__raw_writeq(delta - 1, init);
79	__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
80
81	return 0;
82}
83
84static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
85{
86	unsigned int cpu = smp_processor_id();
87	struct clock_event_device *cd = dev_id;
88	void __iomem *cfg;
89	unsigned long tmode;
90
91	if (clockevent_state_periodic(cd))
92		tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
93	else
94		tmode = 0;
95
96	/* ACK interrupt */
97	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
98	____raw_writeq(tmode, cfg);
99
100	cd->event_handler(cd);
101
102	return IRQ_HANDLED;
103}
104
105static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
106static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
107static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
108
109void sb1250_clockevent_init(void)
110{
111	unsigned int cpu = smp_processor_id();
112	unsigned int irq = K_INT_TIMER_0 + cpu;
113	struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
114	struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
115	unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
116
117	/* Only have 4 general purpose timers, and we use last one as hpt */
118	BUG_ON(cpu > 2);
119
120	sprintf(name, "sb1250-counter-%d", cpu);
121	cd->name		= name;
122	cd->features		= CLOCK_EVT_FEAT_PERIODIC |
123				  CLOCK_EVT_FEAT_ONESHOT;
124	clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
125	cd->max_delta_ns	= clockevent_delta2ns(0x7fffff, cd);
126	cd->min_delta_ns	= clockevent_delta2ns(2, cd);
127	cd->rating		= 200;
128	cd->irq			= irq;
129	cd->cpumask		= cpumask_of(cpu);
130	cd->set_next_event	= sibyte_next_event;
131	cd->set_state_shutdown	= sibyte_shutdown;
132	cd->set_state_periodic	= sibyte_set_periodic;
133	cd->set_state_oneshot	= sibyte_shutdown;
134	clockevents_register_device(cd);
135
136	sb1250_mask_irq(cpu, irq);
137
138	/*
139	 * Map the timer interrupt to IP[4] of this cpu
140	 */
141	__raw_writeq(IMR_IP4_VAL,
142		     IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
143			    (irq << 3)));
144
145	sb1250_unmask_irq(cpu, irq);
146
147	action->handler = sibyte_counter_handler;
148	action->flags	= IRQF_PERCPU | IRQF_TIMER;
149	action->name	= name;
150	action->dev_id	= cd;
151
152	irq_set_affinity(irq, cpumask_of(cpu));
153	setup_irq(irq, action);
154}
155