1/* 2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 3 * JZ4740 platform GPIO support 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * You should have received a copy of the GNU General Public License along 11 * with this program; if not, write to the Free Software Foundation, Inc., 12 * 675 Mass Ave, Cambridge, MA 02139, USA. 13 * 14 */ 15 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/init.h> 19 20#include <linux/io.h> 21#include <linux/gpio.h> 22#include <linux/delay.h> 23#include <linux/interrupt.h> 24#include <linux/irqchip/ingenic.h> 25#include <linux/bitops.h> 26 27#include <linux/debugfs.h> 28#include <linux/seq_file.h> 29 30#include <asm/mach-jz4740/base.h> 31#include <asm/mach-jz4740/gpio.h> 32 33#define JZ4740_GPIO_BASE_A (32*0) 34#define JZ4740_GPIO_BASE_B (32*1) 35#define JZ4740_GPIO_BASE_C (32*2) 36#define JZ4740_GPIO_BASE_D (32*3) 37 38#define JZ4740_GPIO_NUM_A 32 39#define JZ4740_GPIO_NUM_B 32 40#define JZ4740_GPIO_NUM_C 31 41#define JZ4740_GPIO_NUM_D 32 42 43#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A) 44#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B) 45#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C) 46#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D) 47 48#define JZ_REG_GPIO_PIN 0x00 49#define JZ_REG_GPIO_DATA 0x10 50#define JZ_REG_GPIO_DATA_SET 0x14 51#define JZ_REG_GPIO_DATA_CLEAR 0x18 52#define JZ_REG_GPIO_MASK 0x20 53#define JZ_REG_GPIO_MASK_SET 0x24 54#define JZ_REG_GPIO_MASK_CLEAR 0x28 55#define JZ_REG_GPIO_PULL 0x30 56#define JZ_REG_GPIO_PULL_SET 0x34 57#define JZ_REG_GPIO_PULL_CLEAR 0x38 58#define JZ_REG_GPIO_FUNC 0x40 59#define JZ_REG_GPIO_FUNC_SET 0x44 60#define JZ_REG_GPIO_FUNC_CLEAR 0x48 61#define JZ_REG_GPIO_SELECT 0x50 62#define JZ_REG_GPIO_SELECT_SET 0x54 63#define JZ_REG_GPIO_SELECT_CLEAR 0x58 64#define JZ_REG_GPIO_DIRECTION 0x60 65#define JZ_REG_GPIO_DIRECTION_SET 0x64 66#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68 67#define JZ_REG_GPIO_TRIGGER 0x70 68#define JZ_REG_GPIO_TRIGGER_SET 0x74 69#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78 70#define JZ_REG_GPIO_FLAG 0x80 71#define JZ_REG_GPIO_FLAG_CLEAR 0x14 72 73#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f) 74#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg)) 75#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg)) 76 77struct jz_gpio_chip { 78 unsigned int irq; 79 unsigned int irq_base; 80 uint32_t edge_trigger_both; 81 82 void __iomem *base; 83 84 struct gpio_chip gpio_chip; 85}; 86 87static struct jz_gpio_chip jz4740_gpio_chips[]; 88 89static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio) 90{ 91 return &jz4740_gpio_chips[gpio >> 5]; 92} 93 94static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip) 95{ 96 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); 97} 98 99static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data) 100{ 101 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 102 return gc->private; 103} 104 105static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) 106{ 107 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg)); 108} 109 110int jz_gpio_set_function(int gpio, enum jz_gpio_function function) 111{ 112 if (function == JZ_GPIO_FUNC_NONE) { 113 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR); 114 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); 115 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); 116 } else { 117 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET); 118 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); 119 switch (function) { 120 case JZ_GPIO_FUNC1: 121 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); 122 break; 123 case JZ_GPIO_FUNC3: 124 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET); 125 case JZ_GPIO_FUNC2: /* Falltrough */ 126 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET); 127 break; 128 default: 129 BUG(); 130 break; 131 } 132 } 133 134 return 0; 135} 136EXPORT_SYMBOL_GPL(jz_gpio_set_function); 137 138int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num) 139{ 140 size_t i; 141 int ret; 142 143 for (i = 0; i < num; ++i, ++request) { 144 ret = gpio_request(request->gpio, request->name); 145 if (ret) 146 goto err; 147 jz_gpio_set_function(request->gpio, request->function); 148 } 149 150 return 0; 151 152err: 153 for (--request; i > 0; --i, --request) { 154 gpio_free(request->gpio); 155 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); 156 } 157 158 return ret; 159} 160EXPORT_SYMBOL_GPL(jz_gpio_bulk_request); 161 162void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num) 163{ 164 size_t i; 165 166 for (i = 0; i < num; ++i, ++request) { 167 gpio_free(request->gpio); 168 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); 169 } 170 171} 172EXPORT_SYMBOL_GPL(jz_gpio_bulk_free); 173 174void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num) 175{ 176 size_t i; 177 178 for (i = 0; i < num; ++i, ++request) { 179 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); 180 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR); 181 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET); 182 } 183} 184EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend); 185 186void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num) 187{ 188 size_t i; 189 190 for (i = 0; i < num; ++i, ++request) 191 jz_gpio_set_function(request->gpio, request->function); 192} 193EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume); 194 195void jz_gpio_enable_pullup(unsigned gpio) 196{ 197 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR); 198} 199EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup); 200 201void jz_gpio_disable_pullup(unsigned gpio) 202{ 203 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET); 204} 205EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup); 206 207static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio) 208{ 209 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio)); 210} 211 212static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) 213{ 214 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET); 215 reg += !value; 216 writel(BIT(gpio), reg); 217} 218 219static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 220 int value) 221{ 222 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET)); 223 jz_gpio_set_value(chip, gpio, value); 224 225 return 0; 226} 227 228static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 229{ 230 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR)); 231 232 return 0; 233} 234 235static int jz_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 236{ 237 struct jz_gpio_chip *jz_gpio = gpio_chip_to_jz_gpio_chip(chip); 238 239 return jz_gpio->irq_base + gpio; 240} 241 242int jz_gpio_port_direction_input(int port, uint32_t mask) 243{ 244 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR)); 245 246 return 0; 247} 248EXPORT_SYMBOL(jz_gpio_port_direction_input); 249 250int jz_gpio_port_direction_output(int port, uint32_t mask) 251{ 252 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET)); 253 254 return 0; 255} 256EXPORT_SYMBOL(jz_gpio_port_direction_output); 257 258void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask) 259{ 260 writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR)); 261 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET)); 262} 263EXPORT_SYMBOL(jz_gpio_port_set_value); 264 265uint32_t jz_gpio_port_get_value(int port, uint32_t mask) 266{ 267 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN)); 268 269 return value & mask; 270} 271EXPORT_SYMBOL(jz_gpio_port_get_value); 272 273#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f) 274 275static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq) 276{ 277 uint32_t value; 278 void __iomem *reg; 279 uint32_t mask = IRQ_TO_BIT(irq); 280 281 if (!(chip->edge_trigger_both & mask)) 282 return; 283 284 reg = chip->base; 285 286 value = readl(chip->base + JZ_REG_GPIO_PIN); 287 if (value & mask) 288 reg += JZ_REG_GPIO_DIRECTION_CLEAR; 289 else 290 reg += JZ_REG_GPIO_DIRECTION_SET; 291 292 writel(mask, reg); 293} 294 295static void jz_gpio_irq_demux_handler(struct irq_desc *desc) 296{ 297 uint32_t flag; 298 unsigned int gpio_irq; 299 struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); 300 301 flag = readl(chip->base + JZ_REG_GPIO_FLAG); 302 if (!flag) 303 return; 304 305 gpio_irq = chip->irq_base + __fls(flag); 306 307 jz_gpio_check_trigger_both(chip, gpio_irq); 308 309 generic_handle_irq(gpio_irq); 310}; 311 312static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg) 313{ 314 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); 315 writel(IRQ_TO_BIT(data->irq), chip->base + reg); 316} 317 318static void jz_gpio_irq_unmask(struct irq_data *data) 319{ 320 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); 321 322 jz_gpio_check_trigger_both(chip, data->irq); 323 irq_gc_unmask_enable_reg(data); 324}; 325 326/* TODO: Check if function is gpio */ 327static unsigned int jz_gpio_irq_startup(struct irq_data *data) 328{ 329 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET); 330 jz_gpio_irq_unmask(data); 331 return 0; 332} 333 334static void jz_gpio_irq_shutdown(struct irq_data *data) 335{ 336 irq_gc_mask_disable_reg(data); 337 338 /* Set direction to input */ 339 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); 340 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR); 341} 342 343static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) 344{ 345 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); 346 unsigned int irq = data->irq; 347 348 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 349 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); 350 if (value & IRQ_TO_BIT(irq)) 351 flow_type = IRQ_TYPE_EDGE_FALLING; 352 else 353 flow_type = IRQ_TYPE_EDGE_RISING; 354 chip->edge_trigger_both |= IRQ_TO_BIT(irq); 355 } else { 356 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq); 357 } 358 359 switch (flow_type) { 360 case IRQ_TYPE_EDGE_RISING: 361 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); 362 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); 363 break; 364 case IRQ_TYPE_EDGE_FALLING: 365 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); 366 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); 367 break; 368 case IRQ_TYPE_LEVEL_HIGH: 369 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); 370 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); 371 break; 372 case IRQ_TYPE_LEVEL_LOW: 373 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); 374 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); 375 break; 376 default: 377 return -EINVAL; 378 } 379 380 return 0; 381} 382 383static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 384{ 385 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); 386 387 irq_gc_set_wake(data, on); 388 irq_set_irq_wake(chip->irq, on); 389 390 return 0; 391} 392 393#define JZ4740_GPIO_CHIP(_bank) { \ 394 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \ 395 .gpio_chip = { \ 396 .label = "Bank " # _bank, \ 397 .owner = THIS_MODULE, \ 398 .set = jz_gpio_set_value, \ 399 .get = jz_gpio_get_value, \ 400 .direction_output = jz_gpio_direction_output, \ 401 .direction_input = jz_gpio_direction_input, \ 402 .to_irq = jz_gpio_to_irq, \ 403 .base = JZ4740_GPIO_BASE_ ## _bank, \ 404 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ 405 }, \ 406} 407 408static struct jz_gpio_chip jz4740_gpio_chips[] = { 409 JZ4740_GPIO_CHIP(A), 410 JZ4740_GPIO_CHIP(B), 411 JZ4740_GPIO_CHIP(C), 412 JZ4740_GPIO_CHIP(D), 413}; 414 415static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) 416{ 417 struct irq_chip_generic *gc; 418 struct irq_chip_type *ct; 419 420 chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100); 421 422 chip->irq = JZ4740_IRQ_INTC_GPIO(id); 423 irq_set_chained_handler_and_data(chip->irq, 424 jz_gpio_irq_demux_handler, chip); 425 426 gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base, 427 chip->base, handle_level_irq); 428 429 gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio); 430 gc->private = chip; 431 432 ct = gc->chip_types; 433 ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR; 434 ct->regs.disable = JZ_REG_GPIO_MASK_SET; 435 ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR; 436 437 ct->chip.name = "GPIO"; 438 ct->chip.irq_mask = irq_gc_mask_disable_reg; 439 ct->chip.irq_unmask = jz_gpio_irq_unmask; 440 ct->chip.irq_ack = irq_gc_ack_set_bit; 441 ct->chip.irq_suspend = ingenic_intc_irq_suspend; 442 ct->chip.irq_resume = ingenic_intc_irq_resume; 443 ct->chip.irq_startup = jz_gpio_irq_startup; 444 ct->chip.irq_shutdown = jz_gpio_irq_shutdown; 445 ct->chip.irq_set_type = jz_gpio_irq_set_type; 446 ct->chip.irq_set_wake = jz_gpio_irq_set_wake; 447 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; 448 449 irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio), 450 IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL); 451 452 gpiochip_add(&chip->gpio_chip); 453} 454 455static int __init jz4740_gpio_init(void) 456{ 457 unsigned int i; 458 459 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) 460 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); 461 462 printk(KERN_INFO "JZ4740 GPIO initialized\n"); 463 464 return 0; 465} 466arch_initcall(jz4740_gpio_init); 467 468#ifdef CONFIG_DEBUG_FS 469 470static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip, 471 const char *name, unsigned int reg) 472{ 473 seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg)); 474} 475 476static int gpio_regs_show(struct seq_file *s, void *unused) 477{ 478 struct jz_gpio_chip *chip = jz4740_gpio_chips; 479 int i; 480 481 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) { 482 seq_printf(s, "==GPIO %d==\n", i); 483 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN); 484 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA); 485 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK); 486 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL); 487 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC); 488 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT); 489 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION); 490 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER); 491 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG); 492 } 493 494 return 0; 495} 496 497static int gpio_regs_open(struct inode *inode, struct file *file) 498{ 499 return single_open(file, gpio_regs_show, NULL); 500} 501 502static const struct file_operations gpio_regs_operations = { 503 .open = gpio_regs_open, 504 .read = seq_read, 505 .llseek = seq_lseek, 506 .release = single_release, 507}; 508 509static int __init gpio_debugfs_init(void) 510{ 511 (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO, 512 NULL, NULL, &gpio_regs_operations); 513 return 0; 514} 515subsys_initcall(gpio_debugfs_init); 516 517#endif 518