1/* 2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. 3 * 4 * All Alchemy development boards (except, of course, the weird PB1000) 5 * have a few registers in a CPLD with standardised layout; they mostly 6 * only differ in base address and bit meanings in the RESETS and BOARD 7 * registers. 8 * 9 * All data taken from the official AMD board documentation sheets. 10 */ 11 12#ifndef _DB1XXX_BCSR_H_ 13#define _DB1XXX_BCSR_H_ 14 15 16/* BCSR base addresses on various boards. BCSR base 2 refers to the 17 * physical address of the first HEXLEDS register, which is usually 18 * a variable offset from the WHOAMI register. 19 */ 20 21/* DB1000, DB1100, DB1500, PB1100, PB1500 */ 22#define DB1000_BCSR_PHYS_ADDR 0x0E000000 23#define DB1000_BCSR_HEXLED_OFS 0x01000000 24 25#define DB1550_BCSR_PHYS_ADDR 0x0F000000 26#define DB1550_BCSR_HEXLED_OFS 0x00400000 27 28#define PB1550_BCSR_PHYS_ADDR 0x0F000000 29#define PB1550_BCSR_HEXLED_OFS 0x00800000 30 31#define DB1200_BCSR_PHYS_ADDR 0x19800000 32#define DB1200_BCSR_HEXLED_OFS 0x00400000 33 34#define PB1200_BCSR_PHYS_ADDR 0x0D800000 35#define PB1200_BCSR_HEXLED_OFS 0x00400000 36 37#define DB1300_BCSR_PHYS_ADDR 0x19800000 38#define DB1300_BCSR_HEXLED_OFS 0x00400000 39 40enum bcsr_id { 41 /* BCSR base 1 */ 42 BCSR_WHOAMI = 0, 43 BCSR_STATUS, 44 BCSR_SWITCHES, 45 BCSR_RESETS, 46 BCSR_PCMCIA, 47 BCSR_BOARD, 48 BCSR_LEDS, 49 BCSR_SYSTEM, 50 /* Au1200/1300 based boards */ 51 BCSR_INTCLR, 52 BCSR_INTSET, 53 BCSR_MASKCLR, 54 BCSR_MASKSET, 55 BCSR_SIGSTAT, 56 BCSR_INTSTAT, 57 58 /* BCSR base 2 */ 59 BCSR_HEXLEDS, 60 BCSR_RSVD1, 61 BCSR_HEXCLEAR, 62 63 BCSR_CNT, 64}; 65 66/* register offsets, valid for all Db1xxx/Pb1xxx boards */ 67#define BCSR_REG_WHOAMI 0x00 68#define BCSR_REG_STATUS 0x04 69#define BCSR_REG_SWITCHES 0x08 70#define BCSR_REG_RESETS 0x0c 71#define BCSR_REG_PCMCIA 0x10 72#define BCSR_REG_BOARD 0x14 73#define BCSR_REG_LEDS 0x18 74#define BCSR_REG_SYSTEM 0x1c 75/* Au1200/Au1300 based boards: CPLD IRQ muxer */ 76#define BCSR_REG_INTCLR 0x20 77#define BCSR_REG_INTSET 0x24 78#define BCSR_REG_MASKCLR 0x28 79#define BCSR_REG_MASKSET 0x2c 80#define BCSR_REG_SIGSTAT 0x30 81#define BCSR_REG_INTSTAT 0x34 82 83/* hexled control, offset from BCSR base 2 */ 84#define BCSR_REG_HEXLEDS 0x00 85#define BCSR_REG_HEXCLEAR 0x08 86 87/* 88 * Register Bits and Pieces. 89 */ 90#define BCSR_WHOAMI_DCID(x) ((x) & 0xf) 91#define BCSR_WHOAMI_CPLD(x) (((x) >> 4) & 0xf) 92#define BCSR_WHOAMI_BOARD(x) (((x) >> 8) & 0xf) 93 94/* register "WHOAMI" bits 11:8 identify the board */ 95enum bcsr_whoami_boards { 96 BCSR_WHOAMI_PB1500 = 1, 97 BCSR_WHOAMI_PB1500R2, 98 BCSR_WHOAMI_PB1100, 99 BCSR_WHOAMI_DB1000, 100 BCSR_WHOAMI_DB1100, 101 BCSR_WHOAMI_DB1500, 102 BCSR_WHOAMI_DB1550, 103 BCSR_WHOAMI_PB1550_DDR, 104 BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR, 105 BCSR_WHOAMI_PB1550_SDR, 106 BCSR_WHOAMI_PB1200_DDR1, 107 BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, 108 BCSR_WHOAMI_PB1200_DDR2, 109 BCSR_WHOAMI_DB1200, 110 BCSR_WHOAMI_DB1300, 111}; 112 113/* STATUS reg. Unless otherwise noted, they're valid on all boards. 114 * PB1200 = DB1200. 115 */ 116#define BCSR_STATUS_PC0VS 0x0003 117#define BCSR_STATUS_PC1VS 0x000C 118#define BCSR_STATUS_PC0FI 0x0010 119#define BCSR_STATUS_PC1FI 0x0020 120#define BCSR_STATUS_PB1550_SWAPBOOT 0x0040 121#define BCSR_STATUS_SRAMWIDTH 0x0080 122#define BCSR_STATUS_FLASHBUSY 0x0100 123#define BCSR_STATUS_ROMBUSY 0x0400 124#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ 125#define BCSR_STATUS_SD1WP 0x0800 126#define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ 127#define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 128#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ 129#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ 130#define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ 131#define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ 132#define BCSR_STATUS_FLASHDEN 0xC000 133#define BCSR_STATUS_DB1550_U0RXD 0x1000 /* DB1550 */ 134#define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */ 135#define BCSR_STATUS_PB1550_U0RXD 0x1000 /* PB1550 */ 136#define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ 137#define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ 138 139#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ 140#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ 141#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ 142#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ 143#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ 144 145/* DB/PB1000,1100,1500,1550 */ 146#define BCSR_RESETS_PHY0 0x0001 147#define BCSR_RESETS_PHY1 0x0002 148#define BCSR_RESETS_DC 0x0004 149#define BCSR_RESETS_FIR_SEL 0x2000 150#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 151#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 152#define BCSR_RESETS_PB1550_WSCFSM 0x2000 153#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 154#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 155#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 156#define BCSR_RESETS_DMAREQ 0x8000 /* PB1550 */ 157 158#define BCSR_BOARD_PCIM66EN 0x0001 159#define BCSR_BOARD_SD0PWR 0x0040 160#define BCSR_BOARD_SD1PWR 0x0080 161#define BCSR_BOARD_PCIM33 0x0100 162#define BCSR_BOARD_PCIEXTARB 0x0200 163#define BCSR_BOARD_GPIO200RST 0x0400 164#define BCSR_BOARD_PCICLKOUT 0x0800 165#define BCSR_BOARD_PB1100_SD0PWR 0x0400 166#define BCSR_BOARD_PB1100_SD1PWR 0x0800 167#define BCSR_BOARD_PCICFG 0x1000 168#define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */ 169#define BCSR_BOARD_SD0WP 0x4000 /* DB1100 */ 170#define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ 171 172 173/* DB/PB1200/1300 */ 174#define BCSR_RESETS_ETH 0x0001 175#define BCSR_RESETS_CAMERA 0x0002 176#define BCSR_RESETS_DC 0x0004 177#define BCSR_RESETS_IDE 0x0008 178#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ 179/* Not resets but in the same register */ 180#define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ 181#define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ 182#define BCSR_RESETS_PSC0MUX 0x1000 183#define BCSR_RESETS_PSC1MUX 0x2000 184#define BCSR_RESETS_SPISEL 0x4000 185#define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ 186 187#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ 188#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ 189#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ 190#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ 191#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ 192#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ 193#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ 194 195#define BCSR_BOARD_LCDVEE 0x0001 196#define BCSR_BOARD_LCDVDD 0x0002 197#define BCSR_BOARD_LCDBL 0x0004 198#define BCSR_BOARD_CAMSNAP 0x0010 199#define BCSR_BOARD_CAMPWR 0x0020 200#define BCSR_BOARD_SD0PWR 0x0040 201#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ 202#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ 203 204#define BCSR_SWITCHES_DIP 0x00FF 205#define BCSR_SWITCHES_DIP_1 0x0080 206#define BCSR_SWITCHES_DIP_2 0x0040 207#define BCSR_SWITCHES_DIP_3 0x0020 208#define BCSR_SWITCHES_DIP_4 0x0010 209#define BCSR_SWITCHES_DIP_5 0x0008 210#define BCSR_SWITCHES_DIP_6 0x0004 211#define BCSR_SWITCHES_DIP_7 0x0002 212#define BCSR_SWITCHES_DIP_8 0x0001 213#define BCSR_SWITCHES_ROTARY 0x0F00 214 215 216#define BCSR_PCMCIA_PC0VPP 0x0003 217#define BCSR_PCMCIA_PC0VCC 0x000C 218#define BCSR_PCMCIA_PC0DRVEN 0x0010 219#define BCSR_PCMCIA_PC0RST 0x0080 220#define BCSR_PCMCIA_PC1VPP 0x0300 221#define BCSR_PCMCIA_PC1VCC 0x0C00 222#define BCSR_PCMCIA_PC1DRVEN 0x1000 223#define BCSR_PCMCIA_PC1RST 0x8000 224 225 226#define BCSR_LEDS_DECIMALS 0x0003 227#define BCSR_LEDS_LED0 0x0100 228#define BCSR_LEDS_LED1 0x0200 229#define BCSR_LEDS_LED2 0x0400 230#define BCSR_LEDS_LED3 0x0800 231 232 233#define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ 234#define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ 235#define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ 236#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ 237#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ 238#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ 239#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ 240 241 242 243/* initialize BCSR for a board. Provide the PHYSICAL addresses of both 244 * BCSR spaces. 245 */ 246void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys); 247 248/* read a board register */ 249unsigned short bcsr_read(enum bcsr_id reg); 250 251/* write to a board register */ 252void bcsr_write(enum bcsr_id reg, unsigned short val); 253 254/* modify a register. clear bits set in 'clr', set bits set in 'set' */ 255void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); 256 257/* install CPLD IRQ demuxer (DB1200/PB1200) */ 258void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq); 259 260#endif 261