1/*
2 *	DEC I/O ASIC interrupts.
3 *
4 *	Copyright (c) 2002, 2003, 2013  Maciej W. Rozycki
5 *
6 *	This program is free software; you can redistribute it and/or
7 *	modify it under the terms of the GNU General Public License
8 *	as published by the Free Software Foundation; either version
9 *	2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/types.h>
15
16#include <asm/dec/ioasic.h>
17#include <asm/dec/ioasic_addrs.h>
18#include <asm/dec/ioasic_ints.h>
19
20static int ioasic_irq_base;
21
22static void unmask_ioasic_irq(struct irq_data *d)
23{
24	u32 simr;
25
26	simr = ioasic_read(IO_REG_SIMR);
27	simr |= (1 << (d->irq - ioasic_irq_base));
28	ioasic_write(IO_REG_SIMR, simr);
29}
30
31static void mask_ioasic_irq(struct irq_data *d)
32{
33	u32 simr;
34
35	simr = ioasic_read(IO_REG_SIMR);
36	simr &= ~(1 << (d->irq - ioasic_irq_base));
37	ioasic_write(IO_REG_SIMR, simr);
38}
39
40static void ack_ioasic_irq(struct irq_data *d)
41{
42	mask_ioasic_irq(d);
43	fast_iob();
44}
45
46static struct irq_chip ioasic_irq_type = {
47	.name = "IO-ASIC",
48	.irq_ack = ack_ioasic_irq,
49	.irq_mask = mask_ioasic_irq,
50	.irq_mask_ack = ack_ioasic_irq,
51	.irq_unmask = unmask_ioasic_irq,
52};
53
54static void clear_ioasic_dma_irq(struct irq_data *d)
55{
56	u32 sir;
57
58	sir = ~(1 << (d->irq - ioasic_irq_base));
59	ioasic_write(IO_REG_SIR, sir);
60	fast_iob();
61}
62
63static struct irq_chip ioasic_dma_irq_type = {
64	.name = "IO-ASIC-DMA",
65	.irq_ack = clear_ioasic_dma_irq,
66	.irq_mask = mask_ioasic_irq,
67	.irq_unmask = unmask_ioasic_irq,
68	.irq_eoi = clear_ioasic_dma_irq,
69};
70
71/*
72 * I/O ASIC implements two kinds of DMA interrupts, informational and
73 * error interrupts.
74 *
75 * The formers do not stop DMA and should be cleared as soon as possible
76 * so that if they retrigger before the handler has completed, usually as
77 * a side effect of actions taken by the handler, then they are reissued.
78 * These use the `handle_edge_irq' handler that clears the request right
79 * away.
80 *
81 * The latters stop DMA and do not resume it until the interrupt has been
82 * cleared.  This cannot be done until after a corrective action has been
83 * taken and this also means they will not retrigger.  Therefore they use
84 * the `handle_fasteoi_irq' handler that only clears the request on the
85 * way out.  Because MIPS processor interrupt inputs, one of which the I/O
86 * ASIC is cascaded to, are level-triggered it is recommended that error
87 * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
88 * set so that they are run with the interrupt line masked.
89 *
90 * This mask has `1' bits in the positions of informational interrupts.
91 */
92#define IO_IRQ_DMA_INFO							\
93	(IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) |				\
94	 IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) |				\
95	 IO_IRQ_MASK(IO_INR_ISDN_TXDMA) |				\
96	 IO_IRQ_MASK(IO_INR_ISDN_RXDMA) |				\
97	 IO_IRQ_MASK(IO_INR_ASC_DMA))
98
99void __init init_ioasic_irqs(int base)
100{
101	int i;
102
103	/* Mask interrupts. */
104	ioasic_write(IO_REG_SIMR, 0);
105	fast_iob();
106
107	for (i = base; i < base + IO_INR_DMA; i++)
108		irq_set_chip_and_handler(i, &ioasic_irq_type,
109					 handle_level_irq);
110	for (; i < base + IO_IRQ_LINES; i++)
111		irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
112					 1 << (i - base) & IO_IRQ_DMA_INFO ?
113					 handle_edge_irq : handle_fasteoi_irq);
114
115	ioasic_irq_base = base;
116}
117