1/*
2 * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
3 *
4 * Previous incarnations were:
5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
6 * Copied and modified Carsten Langgaard's time.c
7 *
8 * Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
10 *
11 * ########################################################################
12 *
13 *  This program is free software; you can distribute it and/or modify it
14 *  under the terms of the GNU General Public License (Version 2) as
15 *  published by the Free Software Foundation.
16 *
17 *  This program is distributed in the hope it will be useful, but WITHOUT
18 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20 *  for more details.
21 *
22 *  You should have received a copy of the GNU General Public License along
23 *  with this program; if not, write to the Free Software Foundation, Inc.,
24 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
25 *
26 * ########################################################################
27 *
28 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
29 * databooks).  Firmware/Board init code must enable the counters in the
30 * counter control register, otherwise the CP0 counter clocksource/event
31 * will be installed instead (and use of 'wait' instruction is prohibited).
32 */
33
34#include <linux/clockchips.h>
35#include <linux/clocksource.h>
36#include <linux/interrupt.h>
37#include <linux/spinlock.h>
38
39#include <asm/idle.h>
40#include <asm/processor.h>
41#include <asm/time.h>
42#include <asm/mach-au1x00/au1000.h>
43
44/* 32kHz clock enabled and detected */
45#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
46
47static cycle_t au1x_counter1_read(struct clocksource *cs)
48{
49	return alchemy_rdsys(AU1000_SYS_RTCREAD);
50}
51
52static struct clocksource au1x_counter1_clocksource = {
53	.name		= "alchemy-counter1",
54	.read		= au1x_counter1_read,
55	.mask		= CLOCKSOURCE_MASK(32),
56	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
57	.rating		= 1500,
58};
59
60static int au1x_rtcmatch2_set_next_event(unsigned long delta,
61					 struct clock_event_device *cd)
62{
63	delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
64	/* wait for register access */
65	while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
66		;
67	alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
68
69	return 0;
70}
71
72static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
73{
74	struct clock_event_device *cd = dev_id;
75	cd->event_handler(cd);
76	return IRQ_HANDLED;
77}
78
79static struct clock_event_device au1x_rtcmatch2_clockdev = {
80	.name		= "rtcmatch2",
81	.features	= CLOCK_EVT_FEAT_ONESHOT,
82	.rating		= 1500,
83	.set_next_event = au1x_rtcmatch2_set_next_event,
84	.cpumask	= cpu_all_mask,
85};
86
87static struct irqaction au1x_rtcmatch2_irqaction = {
88	.handler	= au1x_rtcmatch2_irq,
89	.flags		= IRQF_TIMER,
90	.name		= "timer",
91	.dev_id		= &au1x_rtcmatch2_clockdev,
92};
93
94static int __init alchemy_time_init(unsigned int m2int)
95{
96	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
97	unsigned long t;
98
99	au1x_rtcmatch2_clockdev.irq = m2int;
100
101	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock
102	 * has been detected.  If so install the rtcmatch2 clocksource,
103	 * otherwise don't bother.  Note that both bits being set is by
104	 * no means a definite guarantee that the counters actually work
105	 * (the 32S bit seems to be stuck set to 1 once a single clock-
106	 * edge is detected, hence the timeouts).
107	 */
108	if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
109		goto cntr_err;
110
111	/*
112	 * setup counter 1 (RTC) to tick at full speed
113	 */
114	t = 0xffffff;
115	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
116		asm volatile ("nop");
117	if (!t)
118		goto cntr_err;
119
120	alchemy_wrsys(0, AU1000_SYS_RTCTRIM);	/* 32.768 kHz */
121
122	t = 0xffffff;
123	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
124		asm volatile ("nop");
125	if (!t)
126		goto cntr_err;
127	alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
128
129	t = 0xffffff;
130	while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
131		asm volatile ("nop");
132	if (!t)
133		goto cntr_err;
134
135	/* register counter1 clocksource and event device */
136	clocksource_register_hz(&au1x_counter1_clocksource, 32768);
137
138	cd->shift = 32;
139	cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
140	cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
141	cd->min_delta_ns = clockevent_delta2ns(9, cd);	/* ~0.28ms */
142	clockevents_register_device(cd);
143	setup_irq(m2int, &au1x_rtcmatch2_irqaction);
144
145	printk(KERN_INFO "Alchemy clocksource installed\n");
146
147	return 0;
148
149cntr_err:
150	return -1;
151}
152
153static int alchemy_m2inttab[] __initdata = {
154	AU1000_RTC_MATCH2_INT,
155	AU1500_RTC_MATCH2_INT,
156	AU1100_RTC_MATCH2_INT,
157	AU1550_RTC_MATCH2_INT,
158	AU1200_RTC_MATCH2_INT,
159	AU1300_RTC_MATCH2_INT,
160};
161
162void __init plat_time_init(void)
163{
164	int t;
165
166	t = alchemy_get_cputype();
167	if (t == ALCHEMY_CPU_UNKNOWN ||
168	    alchemy_time_init(alchemy_m2inttab[t]))
169		cpu_wait = NULL;	/* wait doesn't work with r4k timer */
170}
171