1/*
2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/interrupt.h>
13#include <linux/delay.h>
14#include <linux/sched.h>
15#include <linux/sched_clock.h>
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/timecounter.h>
21#include <asm/cpuinfo.h>
22
23static void __iomem *timer_baseaddr;
24
25static unsigned int freq_div_hz;
26static unsigned int timer_clock_freq;
27
28#define TCSR0	(0x00)
29#define TLR0	(0x04)
30#define TCR0	(0x08)
31#define TCSR1	(0x10)
32#define TLR1	(0x14)
33#define TCR1	(0x18)
34
35#define TCSR_MDT	(1<<0)
36#define TCSR_UDT	(1<<1)
37#define TCSR_GENT	(1<<2)
38#define TCSR_CAPT	(1<<3)
39#define TCSR_ARHT	(1<<4)
40#define TCSR_LOAD	(1<<5)
41#define TCSR_ENIT	(1<<6)
42#define TCSR_ENT	(1<<7)
43#define TCSR_TINT	(1<<8)
44#define TCSR_PWMA	(1<<9)
45#define TCSR_ENALL	(1<<10)
46
47static unsigned int (*read_fn)(void __iomem *);
48static void (*write_fn)(u32, void __iomem *);
49
50static void timer_write32(u32 val, void __iomem *addr)
51{
52	iowrite32(val, addr);
53}
54
55static unsigned int timer_read32(void __iomem *addr)
56{
57	return ioread32(addr);
58}
59
60static void timer_write32_be(u32 val, void __iomem *addr)
61{
62	iowrite32be(val, addr);
63}
64
65static unsigned int timer_read32_be(void __iomem *addr)
66{
67	return ioread32be(addr);
68}
69
70static inline void xilinx_timer0_stop(void)
71{
72	write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
73		 timer_baseaddr + TCSR0);
74}
75
76static inline void xilinx_timer0_start_periodic(unsigned long load_val)
77{
78	if (!load_val)
79		load_val = 1;
80	/* loading value to timer reg */
81	write_fn(load_val, timer_baseaddr + TLR0);
82
83	/* load the initial value */
84	write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
85
86	/* see timer data sheet for detail
87	 * !ENALL - don't enable 'em all
88	 * !PWMA - disable pwm
89	 * TINT - clear interrupt status
90	 * ENT- enable timer itself
91	 * ENIT - enable interrupt
92	 * !LOAD - clear the bit to let go
93	 * ARHT - auto reload
94	 * !CAPT - no external trigger
95	 * !GENT - no external signal
96	 * UDT - set the timer as down counter
97	 * !MDT0 - generate mode
98	 */
99	write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
100		 timer_baseaddr + TCSR0);
101}
102
103static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
104{
105	if (!load_val)
106		load_val = 1;
107	/* loading value to timer reg */
108	write_fn(load_val, timer_baseaddr + TLR0);
109
110	/* load the initial value */
111	write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
112
113	write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
114		 timer_baseaddr + TCSR0);
115}
116
117static int xilinx_timer_set_next_event(unsigned long delta,
118					struct clock_event_device *dev)
119{
120	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
121	xilinx_timer0_start_oneshot(delta);
122	return 0;
123}
124
125static int xilinx_timer_shutdown(struct clock_event_device *evt)
126{
127	pr_info("%s\n", __func__);
128	xilinx_timer0_stop();
129	return 0;
130}
131
132static int xilinx_timer_set_periodic(struct clock_event_device *evt)
133{
134	pr_info("%s\n", __func__);
135	xilinx_timer0_start_periodic(freq_div_hz);
136	return 0;
137}
138
139static struct clock_event_device clockevent_xilinx_timer = {
140	.name			= "xilinx_clockevent",
141	.features		= CLOCK_EVT_FEAT_ONESHOT |
142				  CLOCK_EVT_FEAT_PERIODIC,
143	.shift			= 8,
144	.rating			= 300,
145	.set_next_event		= xilinx_timer_set_next_event,
146	.set_state_shutdown	= xilinx_timer_shutdown,
147	.set_state_periodic	= xilinx_timer_set_periodic,
148};
149
150static inline void timer_ack(void)
151{
152	write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
153}
154
155static irqreturn_t timer_interrupt(int irq, void *dev_id)
156{
157	struct clock_event_device *evt = &clockevent_xilinx_timer;
158#ifdef CONFIG_HEART_BEAT
159	microblaze_heartbeat();
160#endif
161	timer_ack();
162	evt->event_handler(evt);
163	return IRQ_HANDLED;
164}
165
166static struct irqaction timer_irqaction = {
167	.handler = timer_interrupt,
168	.flags = IRQF_TIMER,
169	.name = "timer",
170	.dev_id = &clockevent_xilinx_timer,
171};
172
173static __init void xilinx_clockevent_init(void)
174{
175	clockevent_xilinx_timer.mult =
176		div_sc(timer_clock_freq, NSEC_PER_SEC,
177				clockevent_xilinx_timer.shift);
178	clockevent_xilinx_timer.max_delta_ns =
179		clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer);
180	clockevent_xilinx_timer.min_delta_ns =
181		clockevent_delta2ns(1, &clockevent_xilinx_timer);
182	clockevent_xilinx_timer.cpumask = cpumask_of(0);
183	clockevents_register_device(&clockevent_xilinx_timer);
184}
185
186static u64 xilinx_clock_read(void)
187{
188	return read_fn(timer_baseaddr + TCR1);
189}
190
191static cycle_t xilinx_read(struct clocksource *cs)
192{
193	/* reading actual value of timer 1 */
194	return (cycle_t)xilinx_clock_read();
195}
196
197static struct timecounter xilinx_tc = {
198	.cc = NULL,
199};
200
201static cycle_t xilinx_cc_read(const struct cyclecounter *cc)
202{
203	return xilinx_read(NULL);
204}
205
206static struct cyclecounter xilinx_cc = {
207	.read = xilinx_cc_read,
208	.mask = CLOCKSOURCE_MASK(32),
209	.shift = 8,
210};
211
212static int __init init_xilinx_timecounter(void)
213{
214	xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
215				xilinx_cc.shift);
216
217	timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock());
218
219	return 0;
220}
221
222static struct clocksource clocksource_microblaze = {
223	.name		= "xilinx_clocksource",
224	.rating		= 300,
225	.read		= xilinx_read,
226	.mask		= CLOCKSOURCE_MASK(32),
227	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
228};
229
230static int __init xilinx_clocksource_init(void)
231{
232	if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq))
233		panic("failed to register clocksource");
234
235	/* stop timer1 */
236	write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
237		 timer_baseaddr + TCSR1);
238	/* start timer1 - up counting without interrupt */
239	write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
240
241	/* register timecounter - for ftrace support */
242	init_xilinx_timecounter();
243	return 0;
244}
245
246static void __init xilinx_timer_init(struct device_node *timer)
247{
248	struct clk *clk;
249	static int initialized;
250	u32 irq;
251	u32 timer_num = 1;
252
253	if (initialized)
254		return;
255
256	initialized = 1;
257
258	timer_baseaddr = of_iomap(timer, 0);
259	if (!timer_baseaddr) {
260		pr_err("ERROR: invalid timer base address\n");
261		BUG();
262	}
263
264	write_fn = timer_write32;
265	read_fn = timer_read32;
266
267	write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
268	if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
269		write_fn = timer_write32_be;
270		read_fn = timer_read32_be;
271	}
272
273	irq = irq_of_parse_and_map(timer, 0);
274
275	of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
276	if (timer_num) {
277		pr_emerg("Please enable two timers in HW\n");
278		BUG();
279	}
280
281	pr_info("%s: irq=%d\n", timer->full_name, irq);
282
283	clk = of_clk_get(timer, 0);
284	if (IS_ERR(clk)) {
285		pr_err("ERROR: timer CCF input clock not found\n");
286		/* If there is clock-frequency property than use it */
287		of_property_read_u32(timer, "clock-frequency",
288				    &timer_clock_freq);
289	} else {
290		timer_clock_freq = clk_get_rate(clk);
291	}
292
293	if (!timer_clock_freq) {
294		pr_err("ERROR: Using CPU clock frequency\n");
295		timer_clock_freq = cpuinfo.cpu_clock_freq;
296	}
297
298	freq_div_hz = timer_clock_freq / HZ;
299
300	setup_irq(irq, &timer_irqaction);
301#ifdef CONFIG_HEART_BEAT
302	microblaze_setup_heartbeat();
303#endif
304	xilinx_clocksource_init();
305	xilinx_clockevent_init();
306
307	sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
308}
309
310CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
311		       xilinx_timer_init);
312