1/***************************************************************************/ 2 3/* 4 * m5249.c -- platform support for ColdFire 5249 based boards 5 * 6 * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com) 7 */ 8 9/***************************************************************************/ 10 11#include <linux/kernel.h> 12#include <linux/param.h> 13#include <linux/init.h> 14#include <linux/io.h> 15#include <linux/platform_device.h> 16#include <asm/machdep.h> 17#include <asm/coldfire.h> 18#include <asm/mcfsim.h> 19#include <asm/mcfclk.h> 20 21/***************************************************************************/ 22 23DEFINE_CLK(pll, "pll.0", MCF_CLK); 24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK); 26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); 27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 30 31struct clk *mcf_clks[] = { 32 &clk_pll, 33 &clk_sys, 34 &clk_mcftmr0, 35 &clk_mcftmr1, 36 &clk_mcfuart0, 37 &clk_mcfuart1, 38 &clk_mcfqspi0, 39 NULL 40}; 41 42/***************************************************************************/ 43 44#ifdef CONFIG_M5249C3 45 46static struct resource m5249_smc91x_resources[] = { 47 { 48 .start = 0xe0000300, 49 .end = 0xe0000300 + 0x100, 50 .flags = IORESOURCE_MEM, 51 }, 52 { 53 .start = MCF_IRQ_GPIO6, 54 .end = MCF_IRQ_GPIO6, 55 .flags = IORESOURCE_IRQ, 56 }, 57}; 58 59static struct platform_device m5249_smc91x = { 60 .name = "smc91x", 61 .id = 0, 62 .num_resources = ARRAY_SIZE(m5249_smc91x_resources), 63 .resource = m5249_smc91x_resources, 64}; 65 66#endif /* CONFIG_M5249C3 */ 67 68static struct platform_device *m5249_devices[] __initdata = { 69#ifdef CONFIG_M5249C3 70 &m5249_smc91x, 71#endif 72}; 73 74/***************************************************************************/ 75 76static void __init m5249_qspi_init(void) 77{ 78#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 79 /* QSPI irq setup */ 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, 81 MCFSIM_QSPIICR); 82 mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); 83#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 84} 85 86/***************************************************************************/ 87 88#ifdef CONFIG_M5249C3 89 90static void __init m5249_smc91x_init(void) 91{ 92 u32 gpio; 93 94 /* Set the GPIO line as interrupt source for smc91x device */ 95 gpio = readl(MCFSIM2_GPIOINTENABLE); 96 writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE); 97 98 gpio = readl(MCFINTC2_INTPRI5); 99 writel(gpio | 0x04000000, MCFINTC2_INTPRI5); 100} 101 102#endif /* CONFIG_M5249C3 */ 103 104/***************************************************************************/ 105 106void __init config_BSP(char *commandp, int size) 107{ 108 mach_sched_init = hw_timer_init; 109 110#ifdef CONFIG_M5249C3 111 m5249_smc91x_init(); 112#endif 113 m5249_qspi_init(); 114} 115 116/***************************************************************************/ 117 118static int __init init_BSP(void) 119{ 120 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); 121 return 0; 122} 123 124arch_initcall(init_BSP); 125 126/***************************************************************************/ 127