1/* File: arch/blackfin/mach-bf527/boards/tll6527m.c 2 * Based on: arch/blackfin/mach-bf527/boards/ezkit.c 3 * Author: Ashish Gupta 4 * 5 * Copyright: 2010 - The Learning Labs Inc. 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10#include <linux/device.h> 11#include <linux/export.h> 12#include <linux/platform_device.h> 13#include <linux/mtd/mtd.h> 14#include <linux/mtd/partitions.h> 15#include <linux/mtd/physmap.h> 16#include <linux/spi/spi.h> 17#include <linux/spi/flash.h> 18#include <linux/i2c.h> 19#include <linux/irq.h> 20#include <linux/interrupt.h> 21#include <linux/usb/musb.h> 22#include <linux/leds.h> 23#include <linux/input.h> 24#include <asm/dma.h> 25#include <asm/bfin5xx_spi.h> 26#include <asm/reboot.h> 27#include <asm/nand.h> 28#include <asm/portmux.h> 29#include <asm/dpmc.h> 30 31#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) 32#include <linux/spi/ad7879.h> 33#define LCD_BACKLIGHT_GPIO 0x40 34/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for 35 * LCD Backlight Enable 36 */ 37#endif 38 39/* 40 * Name the Board for the /proc/cpuinfo 41 */ 42const char bfin_board_name[] = "TLL6527M"; 43/* 44 * Driver needs to know address, irq and flag pin. 45 */ 46 47#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) 48static struct resource musb_resources[] = { 49 [0] = { 50 .start = 0xffc03800, 51 .end = 0xffc03cff, 52 .flags = IORESOURCE_MEM, 53 }, 54 [1] = { /* general IRQ */ 55 .start = IRQ_USB_INT0, 56 .end = IRQ_USB_INT0, 57 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 58 }, 59 [2] = { /* DMA IRQ */ 60 .start = IRQ_USB_DMA, 61 .end = IRQ_USB_DMA, 62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 63 }, 64}; 65 66static struct musb_hdrc_config musb_config = { 67 .multipoint = 0, 68 .dyn_fifo = 0, 69 .soft_con = 1, 70 .dma = 1, 71 .num_eps = 8, 72 .dma_channels = 8, 73 /*.gpio_vrsel = GPIO_PG13,*/ 74 /* Some custom boards need to be active low, just set it to "0" 75 * if it is the case. 76 */ 77 .gpio_vrsel_active = 1, 78}; 79 80static struct musb_hdrc_platform_data musb_plat = { 81#if defined(CONFIG_USB_MUSB_OTG) 82 .mode = MUSB_OTG, 83#elif defined(CONFIG_USB_MUSB_HDRC_HCD) 84 .mode = MUSB_HOST, 85#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 86 .mode = MUSB_PERIPHERAL, 87#endif 88 .config = &musb_config, 89}; 90 91static u64 musb_dmamask = ~(u32)0; 92 93static struct platform_device musb_device = { 94 .name = "musb-blackfin", 95 .id = 0, 96 .dev = { 97 .dma_mask = &musb_dmamask, 98 .coherent_dma_mask = 0xffffffff, 99 .platform_data = &musb_plat, 100 }, 101 .num_resources = ARRAY_SIZE(musb_resources), 102 .resource = musb_resources, 103}; 104#endif 105 106#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) 107#include <asm/bfin-lq035q1.h> 108 109static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = { 110 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB, 111 .ppi_mode = USE_RGB565_16_BIT_PPI, 112 .use_bl = 1, 113 .gpio_bl = LCD_BACKLIGHT_GPIO, 114}; 115 116static struct resource bfin_lq035q1_resources[] = { 117 { 118 .start = IRQ_PPI_ERROR, 119 .end = IRQ_PPI_ERROR, 120 .flags = IORESOURCE_IRQ, 121 }, 122}; 123 124static struct platform_device bfin_lq035q1_device = { 125 .name = "bfin-lq035q1", 126 .id = -1, 127 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources), 128 .resource = bfin_lq035q1_resources, 129 .dev = { 130 .platform_data = &bfin_lq035q1_data, 131 }, 132}; 133#endif 134 135#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) 136static struct mtd_partition tll6527m_partitions[] = { 137 { 138 .name = "bootloader(nor)", 139 .size = 0xA0000, 140 .offset = 0, 141 }, { 142 .name = "linux kernel(nor)", 143 .size = 0xD00000, 144 .offset = MTDPART_OFS_APPEND, 145 }, { 146 .name = "file system(nor)", 147 .size = MTDPART_SIZ_FULL, 148 .offset = MTDPART_OFS_APPEND, 149 } 150}; 151 152static struct physmap_flash_data tll6527m_flash_data = { 153 .width = 2, 154 .parts = tll6527m_partitions, 155 .nr_parts = ARRAY_SIZE(tll6527m_partitions), 156}; 157 158static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 }; 159 160static struct resource tll6527m_flash_resource[] = { 161 { 162 .name = "cfi_probe", 163 .start = 0x20000000, 164 .end = 0x201fffff, 165 .flags = IORESOURCE_MEM, 166 }, { 167 .start = (unsigned long)tll6527m_flash_gpios, 168 .end = ARRAY_SIZE(tll6527m_flash_gpios), 169 .flags = IORESOURCE_IRQ, 170 } 171}; 172 173static struct platform_device tll6527m_flash_device = { 174 .name = "gpio-addr-flash", 175 .id = 0, 176 .dev = { 177 .platform_data = &tll6527m_flash_data, 178 }, 179 .num_resources = ARRAY_SIZE(tll6527m_flash_resource), 180 .resource = tll6527m_flash_resource, 181}; 182#endif 183 184#if IS_ENABLED(CONFIG_GPIO_DECODER) 185/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented 186 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0. 187 * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being 188 * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS 189 */ 190#include <linux/gpio-decoder.h> 191#define EXP_GPIO_SPISEL_BASE 0x64 192static unsigned gpio_addr_inputs[] = { 193 GPIO_PG1, GPIO_PH9, GPIO_PH10 194}; 195 196static struct gpio_decoder_platform_data spi_decoded_cs = { 197 .base = EXP_GPIO_SPISEL_BASE, 198 .input_addrs = gpio_addr_inputs, 199 .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs), 200 .default_output = 0, 201/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */ 202}; 203 204static struct platform_device spi_decoded_gpio = { 205 .name = "gpio-decoder", 206 .id = 0, 207 .dev = { 208 .platform_data = &spi_decoded_cs, 209 }, 210}; 211 212#else 213#define EXP_GPIO_SPISEL_BASE 0x0 214 215#endif 216 217#if IS_ENABLED(CONFIG_INPUT_ADXL34X) 218#include <linux/input/adxl34x.h> 219static const struct adxl34x_platform_data adxl345_info = { 220 .x_axis_offset = 0, 221 .y_axis_offset = 0, 222 .z_axis_offset = 0, 223 .tap_threshold = 0x31, 224 .tap_duration = 0x10, 225 .tap_latency = 0x60, 226 .tap_window = 0xF0, 227 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, 228 .act_axis_control = 0xFF, 229 .activity_threshold = 5, 230 .inactivity_threshold = 2, 231 .inactivity_time = 2, 232 .free_fall_threshold = 0x7, 233 .free_fall_time = 0x20, 234 .data_rate = 0x8, 235 .data_range = ADXL_FULL_RES, 236 237 .ev_type = EV_ABS, 238 .ev_code_x = ABS_X, /* EV_REL */ 239 .ev_code_y = ABS_Y, /* EV_REL */ 240 .ev_code_z = ABS_Z, /* EV_REL */ 241 242 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ 243 244/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ 245 .ev_code_act_inactivity = KEY_A, /* EV_KEY */ 246 .use_int2 = 1, 247 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, 248 .fifo_mode = ADXL_FIFO_STREAM, 249}; 250#endif 251 252#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) 253static struct platform_device rtc_device = { 254 .name = "rtc-bfin", 255 .id = -1, 256}; 257#endif 258 259#if IS_ENABLED(CONFIG_BFIN_MAC) 260#include <linux/bfin_mac.h> 261static const unsigned short bfin_mac_peripherals[] = P_RMII0; 262 263static struct bfin_phydev_platform_data bfin_phydev_data[] = { 264 { 265 .addr = 1, 266 .irq = IRQ_MAC_PHYINT, 267 }, 268}; 269 270static struct bfin_mii_bus_platform_data bfin_mii_bus_data = { 271 .phydev_number = 1, 272 .phydev_data = bfin_phydev_data, 273 .phy_mode = PHY_INTERFACE_MODE_RMII, 274 .mac_peripherals = bfin_mac_peripherals, 275}; 276 277static struct platform_device bfin_mii_bus = { 278 .name = "bfin_mii_bus", 279 .dev = { 280 .platform_data = &bfin_mii_bus_data, 281 } 282}; 283 284static struct platform_device bfin_mac_device = { 285 .name = "bfin_mac", 286 .dev = { 287 .platform_data = &bfin_mii_bus, 288 } 289}; 290#endif 291 292#if IS_ENABLED(CONFIG_MTD_M25P80) 293static struct mtd_partition bfin_spi_flash_partitions[] = { 294 { 295 .name = "bootloader(spi)", 296 .size = 0x00040000, 297 .offset = 0, 298 .mask_flags = MTD_CAP_ROM 299 }, { 300 .name = "linux kernel(spi)", 301 .size = MTDPART_SIZ_FULL, 302 .offset = MTDPART_OFS_APPEND, 303 } 304}; 305 306static struct flash_platform_data bfin_spi_flash_data = { 307 .name = "m25p80", 308 .parts = bfin_spi_flash_partitions, 309 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), 310 .type = "m25p16", 311}; 312 313/* SPI flash chip (m25p64) */ 314static struct bfin5xx_spi_chip spi_flash_chip_info = { 315 .enable_dma = 0, /* use dma transfer with this chip*/ 316}; 317#endif 318 319#if IS_ENABLED(CONFIG_MMC_SPI) 320static struct bfin5xx_spi_chip mmc_spi_chip_info = { 321 .enable_dma = 0, 322}; 323#endif 324 325#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879) 326static const struct ad7879_platform_data bfin_ad7879_ts_info = { 327 .model = 7879, /* Model = AD7879 */ 328 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */ 329 .pressure_max = 10000, 330 .pressure_min = 0, 331 .first_conversion_delay = 3, 332 /* wait 512us before do a first conversion */ 333 .acquisition_time = 1, /* 4us acquisition time per sample */ 334 .median = 2, /* do 8 measurements */ 335 .averaging = 1, 336 /* take the average of 4 middle samples */ 337 .pen_down_acc_interval = 255, /* 9.4 ms */ 338 .gpio_export = 1, /* configure AUX as GPIO output*/ 339 .gpio_base = LCD_BACKLIGHT_GPIO, 340}; 341#endif 342 343#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 344static struct platform_device bfin_i2s = { 345 .name = "bfin-i2s", 346 .id = CONFIG_SND_BF5XX_SPORT_NUM, 347 /* TODO: add platform data here */ 348}; 349#endif 350 351#if IS_ENABLED(CONFIG_GPIO_MCP23S08) 352#include <linux/spi/mcp23s08.h> 353static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { 354 .chip[0].is_present = true, 355 .base = 0x30, 356}; 357static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = { 358 .chip[2].is_present = true, 359 .base = 0x38, 360}; 361#endif 362 363static struct spi_board_info bfin_spi_board_info[] __initdata = { 364#if IS_ENABLED(CONFIG_MTD_M25P80) 365 { 366 /* the modalias must be the same as spi device driver name */ 367 .modalias = "m25p80", /* Name of spi_driver for this device */ 368 .max_speed_hz = 25000000, 369 /* max spi clock (SCK) speed in HZ */ 370 .bus_num = 0, /* Framework bus number */ 371 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS, 372 /* Can be connected to TLL6527M GPIO connector */ 373 /* Either SPI_ADC or M25P80 FLASH can be installed at a time */ 374 .platform_data = &bfin_spi_flash_data, 375 .controller_data = &spi_flash_chip_info, 376 .mode = SPI_MODE_3, 377 }, 378#endif 379 380#if IS_ENABLED(CONFIG_MMC_SPI) 381 { 382 .modalias = "mmc_spi", 383/* 384 * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to 385 * SPI buffer limitations 386 */ 387 .max_speed_hz = 10000000, 388 /* max spi clock (SCK) speed in HZ */ 389 .bus_num = 0, 390 .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS, 391 .controller_data = &mmc_spi_chip_info, 392 .mode = SPI_MODE_0, 393 }, 394#endif 395#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI) 396 { 397 .modalias = "ad7879", 398 .platform_data = &bfin_ad7879_ts_info, 399 .irq = IRQ_PH14, 400 .max_speed_hz = 5000000, 401 /* max spi clock (SCK) speed in HZ */ 402 .bus_num = 0, 403 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS, 404 .mode = SPI_CPHA | SPI_CPOL, 405 }, 406#endif 407#if IS_ENABLED(CONFIG_SPI_SPIDEV) 408 { 409 .modalias = "spidev", 410 .max_speed_hz = 10000000, 411 /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */ 412 .bus_num = 0, 413 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS, 414 .mode = SPI_CPHA | SPI_CPOL, 415 }, 416#endif 417#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) 418 { 419 .modalias = "bfin-lq035q1-spi", 420 .max_speed_hz = 20000000, 421 .bus_num = 0, 422 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS, 423 .mode = SPI_CPHA | SPI_CPOL, 424 }, 425#endif 426#if IS_ENABLED(CONFIG_GPIO_MCP23S08) 427 { 428 .modalias = "mcp23s08", 429 .platform_data = &bfin_mcp23s08_sys_gpio_info, 430 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 431 .bus_num = 0, 432 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS, 433 .mode = SPI_CPHA | SPI_CPOL, 434 }, 435 { 436 .modalias = "mcp23s08", 437 .platform_data = &bfin_mcp23s08_usr_gpio_info, 438 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 439 .bus_num = 0, 440 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS, 441 .mode = SPI_CPHA | SPI_CPOL, 442 }, 443#endif 444}; 445 446#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 447/* SPI controller data */ 448static struct bfin5xx_spi_master bfin_spi0_info = { 449 .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS, 450 /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */ 451 .enable_dma = 1, /* master has the ability to do dma transfer */ 452 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 453}; 454 455/* SPI (0) */ 456static struct resource bfin_spi0_resource[] = { 457 [0] = { 458 .start = SPI0_REGBASE, 459 .end = SPI0_REGBASE + 0xFF, 460 .flags = IORESOURCE_MEM, 461 }, 462 [1] = { 463 .start = CH_SPI, 464 .end = CH_SPI, 465 .flags = IORESOURCE_DMA, 466 }, 467 [2] = { 468 .start = IRQ_SPI, 469 .end = IRQ_SPI, 470 .flags = IORESOURCE_IRQ, 471 }, 472}; 473 474static struct platform_device bfin_spi0_device = { 475 .name = "bfin-spi", 476 .id = 0, /* Bus number */ 477 .num_resources = ARRAY_SIZE(bfin_spi0_resource), 478 .resource = bfin_spi0_resource, 479 .dev = { 480 .platform_data = &bfin_spi0_info, /* Passed to driver */ 481 }, 482}; 483#endif /* spi master and devices */ 484 485#if IS_ENABLED(CONFIG_SERIAL_BFIN) 486#ifdef CONFIG_SERIAL_BFIN_UART0 487static struct resource bfin_uart0_resources[] = { 488 { 489 .start = UART0_THR, 490 .end = UART0_GCTL+2, 491 .flags = IORESOURCE_MEM, 492 }, 493 { 494 .start = IRQ_UART0_TX, 495 .end = IRQ_UART0_TX, 496 .flags = IORESOURCE_IRQ, 497 }, 498 { 499 .start = IRQ_UART0_RX, 500 .end = IRQ_UART0_RX, 501 .flags = IORESOURCE_IRQ, 502 }, 503 { 504 .start = IRQ_UART0_ERROR, 505 .end = IRQ_UART0_ERROR, 506 .flags = IORESOURCE_IRQ, 507 }, 508 { 509 .start = CH_UART0_TX, 510 .end = CH_UART0_TX, 511 .flags = IORESOURCE_DMA, 512 }, 513 { 514 .start = CH_UART0_RX, 515 .end = CH_UART0_RX, 516 .flags = IORESOURCE_DMA, 517 }, 518}; 519 520static unsigned short bfin_uart0_peripherals[] = { 521 P_UART0_TX, P_UART0_RX, 0 522}; 523 524static struct platform_device bfin_uart0_device = { 525 .name = "bfin-uart", 526 .id = 0, 527 .num_resources = ARRAY_SIZE(bfin_uart0_resources), 528 .resource = bfin_uart0_resources, 529 .dev = { 530 .platform_data = &bfin_uart0_peripherals, 531 /* Passed to driver */ 532 }, 533}; 534#endif 535#ifdef CONFIG_SERIAL_BFIN_UART1 536static struct resource bfin_uart1_resources[] = { 537 { 538 .start = UART1_THR, 539 .end = UART1_GCTL+2, 540 .flags = IORESOURCE_MEM, 541 }, 542 { 543 .start = IRQ_UART1_TX, 544 .end = IRQ_UART1_TX, 545 .flags = IORESOURCE_IRQ, 546 }, 547 { 548 .start = IRQ_UART1_RX, 549 .end = IRQ_UART1_RX, 550 .flags = IORESOURCE_IRQ, 551 }, 552 { 553 .start = IRQ_UART1_ERROR, 554 .end = IRQ_UART1_ERROR, 555 .flags = IORESOURCE_IRQ, 556 }, 557 { 558 .start = CH_UART1_TX, 559 .end = CH_UART1_TX, 560 .flags = IORESOURCE_DMA, 561 }, 562 { 563 .start = CH_UART1_RX, 564 .end = CH_UART1_RX, 565 .flags = IORESOURCE_DMA, 566 }, 567#ifdef CONFIG_BFIN_UART1_CTSRTS 568 { /* CTS pin */ 569 .start = GPIO_PF9, 570 .end = GPIO_PF9, 571 .flags = IORESOURCE_IO, 572 }, 573 { /* RTS pin */ 574 .start = GPIO_PF10, 575 .end = GPIO_PF10, 576 .flags = IORESOURCE_IO, 577 }, 578#endif 579}; 580 581static unsigned short bfin_uart1_peripherals[] = { 582 P_UART1_TX, P_UART1_RX, 0 583}; 584 585static struct platform_device bfin_uart1_device = { 586 .name = "bfin-uart", 587 .id = 1, 588 .num_resources = ARRAY_SIZE(bfin_uart1_resources), 589 .resource = bfin_uart1_resources, 590 .dev = { 591 .platform_data = &bfin_uart1_peripherals, 592 /* Passed to driver */ 593 }, 594}; 595#endif 596#endif 597 598#if IS_ENABLED(CONFIG_BFIN_SIR) 599#ifdef CONFIG_BFIN_SIR0 600static struct resource bfin_sir0_resources[] = { 601 { 602 .start = 0xFFC00400, 603 .end = 0xFFC004FF, 604 .flags = IORESOURCE_MEM, 605 }, 606 { 607 .start = IRQ_UART0_RX, 608 .end = IRQ_UART0_RX+1, 609 .flags = IORESOURCE_IRQ, 610 }, 611 { 612 .start = CH_UART0_RX, 613 .end = CH_UART0_RX+1, 614 .flags = IORESOURCE_DMA, 615 }, 616}; 617 618static struct platform_device bfin_sir0_device = { 619 .name = "bfin_sir", 620 .id = 0, 621 .num_resources = ARRAY_SIZE(bfin_sir0_resources), 622 .resource = bfin_sir0_resources, 623}; 624#endif 625#ifdef CONFIG_BFIN_SIR1 626static struct resource bfin_sir1_resources[] = { 627 { 628 .start = 0xFFC02000, 629 .end = 0xFFC020FF, 630 .flags = IORESOURCE_MEM, 631 }, 632 { 633 .start = IRQ_UART1_RX, 634 .end = IRQ_UART1_RX+1, 635 .flags = IORESOURCE_IRQ, 636 }, 637 { 638 .start = CH_UART1_RX, 639 .end = CH_UART1_RX+1, 640 .flags = IORESOURCE_DMA, 641 }, 642}; 643 644static struct platform_device bfin_sir1_device = { 645 .name = "bfin_sir", 646 .id = 1, 647 .num_resources = ARRAY_SIZE(bfin_sir1_resources), 648 .resource = bfin_sir1_resources, 649}; 650#endif 651#endif 652 653#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) 654static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; 655 656static struct resource bfin_twi0_resource[] = { 657 [0] = { 658 .start = TWI0_REGBASE, 659 .end = TWI0_REGBASE, 660 .flags = IORESOURCE_MEM, 661 }, 662 [1] = { 663 .start = IRQ_TWI, 664 .end = IRQ_TWI, 665 .flags = IORESOURCE_IRQ, 666 }, 667}; 668 669static struct platform_device i2c_bfin_twi_device = { 670 .name = "i2c-bfin-twi", 671 .id = 0, 672 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 673 .resource = bfin_twi0_resource, 674 .dev = { 675 .platform_data = &bfin_twi0_pins, 676 }, 677}; 678#endif 679 680static struct i2c_board_info __initdata bfin_i2c_board_info[] = { 681#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) 682 { 683 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 684 }, 685#endif 686 687#if IS_ENABLED(CONFIG_FB_BFIN_7393) 688 { 689 I2C_BOARD_INFO("bfin-adv7393", 0x2B), 690 }, 691#endif 692#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C) 693 { 694 I2C_BOARD_INFO("ad7879", 0x2C), 695 .irq = IRQ_PH14, 696 .platform_data = (void *)&bfin_ad7879_ts_info, 697 }, 698#endif 699#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) 700 { 701 I2C_BOARD_INFO("ssm2602", 0x1b), 702 }, 703#endif 704 { 705 I2C_BOARD_INFO("adm1192", 0x2e), 706 }, 707 708 { 709 I2C_BOARD_INFO("ltc3576", 0x09), 710 }, 711#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) 712 { 713 I2C_BOARD_INFO("adxl34x", 0x53), 714 .irq = IRQ_PH13, 715 .platform_data = (void *)&adxl345_info, 716 }, 717#endif 718}; 719 720#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) 721#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 722static struct resource bfin_sport0_uart_resources[] = { 723 { 724 .start = SPORT0_TCR1, 725 .end = SPORT0_MRCS3+4, 726 .flags = IORESOURCE_MEM, 727 }, 728 { 729 .start = IRQ_SPORT0_RX, 730 .end = IRQ_SPORT0_RX+1, 731 .flags = IORESOURCE_IRQ, 732 }, 733 { 734 .start = IRQ_SPORT0_ERROR, 735 .end = IRQ_SPORT0_ERROR, 736 .flags = IORESOURCE_IRQ, 737 }, 738}; 739 740static unsigned short bfin_sport0_peripherals[] = { 741 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 742 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 743}; 744 745static struct platform_device bfin_sport0_uart_device = { 746 .name = "bfin-sport-uart", 747 .id = 0, 748 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), 749 .resource = bfin_sport0_uart_resources, 750 .dev = { 751 .platform_data = &bfin_sport0_peripherals, 752 /* Passed to driver */ 753 }, 754}; 755#endif 756#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 757static struct resource bfin_sport1_uart_resources[] = { 758 { 759 .start = SPORT1_TCR1, 760 .end = SPORT1_MRCS3+4, 761 .flags = IORESOURCE_MEM, 762 }, 763 { 764 .start = IRQ_SPORT1_RX, 765 .end = IRQ_SPORT1_RX+1, 766 .flags = IORESOURCE_IRQ, 767 }, 768 { 769 .start = IRQ_SPORT1_ERROR, 770 .end = IRQ_SPORT1_ERROR, 771 .flags = IORESOURCE_IRQ, 772 }, 773}; 774 775static unsigned short bfin_sport1_peripherals[] = { 776 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 777 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 778}; 779 780static struct platform_device bfin_sport1_uart_device = { 781 .name = "bfin-sport-uart", 782 .id = 1, 783 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), 784 .resource = bfin_sport1_uart_resources, 785 .dev = { 786 .platform_data = &bfin_sport1_peripherals, 787 /* Passed to driver */ 788 }, 789}; 790#endif 791#endif 792 793static const unsigned int cclk_vlev_datasheet[] = { 794 VRPAIR(VLEV_100, 400000000), 795 VRPAIR(VLEV_105, 426000000), 796 VRPAIR(VLEV_110, 500000000), 797 VRPAIR(VLEV_115, 533000000), 798 VRPAIR(VLEV_120, 600000000), 799}; 800 801static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 802 .tuple_tab = cclk_vlev_datasheet, 803 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 804 .vr_settling_time = 25 /* us */, 805}; 806 807static struct platform_device bfin_dpmc = { 808 .name = "bfin dpmc", 809 .dev = { 810 .platform_data = &bfin_dmpc_vreg_data, 811 }, 812}; 813 814static struct platform_device *tll6527m_devices[] __initdata = { 815 816 &bfin_dpmc, 817 818#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) 819 &rtc_device, 820#endif 821 822#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) 823 &musb_device, 824#endif 825 826#if IS_ENABLED(CONFIG_BFIN_MAC) 827 &bfin_mii_bus, 828 &bfin_mac_device, 829#endif 830 831#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 832 &bfin_spi0_device, 833#endif 834 835#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1) 836 &bfin_lq035q1_device, 837#endif 838 839#if IS_ENABLED(CONFIG_SERIAL_BFIN) 840#ifdef CONFIG_SERIAL_BFIN_UART0 841 &bfin_uart0_device, 842#endif 843#ifdef CONFIG_SERIAL_BFIN_UART1 844 &bfin_uart1_device, 845#endif 846#endif 847 848#if IS_ENABLED(CONFIG_BFIN_SIR) 849#ifdef CONFIG_BFIN_SIR0 850 &bfin_sir0_device, 851#endif 852#ifdef CONFIG_BFIN_SIR1 853 &bfin_sir1_device, 854#endif 855#endif 856 857#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) 858 &i2c_bfin_twi_device, 859#endif 860 861#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) 862#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 863 &bfin_sport0_uart_device, 864#endif 865#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 866 &bfin_sport1_uart_device, 867#endif 868#endif 869 870#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR) 871 &tll6527m_flash_device, 872#endif 873 874#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 875 &bfin_i2s, 876#endif 877 878#if IS_ENABLED(CONFIG_GPIO_DECODER) 879 &spi_decoded_gpio, 880#endif 881}; 882 883static int __init tll6527m_init(void) 884{ 885 printk(KERN_INFO "%s(): registering device resources\n", __func__); 886 i2c_register_board_info(0, bfin_i2c_board_info, 887 ARRAY_SIZE(bfin_i2c_board_info)); 888 platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices)); 889 spi_register_board_info(bfin_spi_board_info, 890 ARRAY_SIZE(bfin_spi_board_info)); 891 return 0; 892} 893 894arch_initcall(tll6527m_init); 895 896static struct platform_device *tll6527m_early_devices[] __initdata = { 897#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) 898#ifdef CONFIG_SERIAL_BFIN_UART0 899 &bfin_uart0_device, 900#endif 901#ifdef CONFIG_SERIAL_BFIN_UART1 902 &bfin_uart1_device, 903#endif 904#endif 905 906#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE) 907#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 908 &bfin_sport0_uart_device, 909#endif 910#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 911 &bfin_sport1_uart_device, 912#endif 913#endif 914}; 915 916void __init native_machine_early_platform_add_devices(void) 917{ 918 printk(KERN_INFO "register early platform devices\n"); 919 early_platform_add_devices(tll6527m_early_devices, 920 ARRAY_SIZE(tll6527m_early_devices)); 921} 922 923void native_machine_restart(char *cmd) 924{ 925 /* workaround reboot hang when booting from SPI */ 926 if ((bfin_read_SYSCR() & 0x7) == 0x3) 927 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); 928} 929 930int bfin_get_ether_addr(char *addr) 931{ 932 /* the MAC is stored in OTP memory page 0xDF */ 933 u32 ret; 934 u64 otp_mac; 935 u32 (*otp_read)(u32 page, u32 flags, 936 u64 *page_content) = (void *)0xEF00001A; 937 938 ret = otp_read(0xDF, 0x00, &otp_mac); 939 if (!(ret & 0x1)) { 940 char *otp_mac_p = (char *)&otp_mac; 941 for (ret = 0; ret < 6; ++ret) 942 addr[ret] = otp_mac_p[5 - ret]; 943 } 944 return 0; 945} 946EXPORT_SYMBOL(bfin_get_ether_addr); 947