1/*
2 * Record and handle CPU attributes.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17#include <asm/arch_timer.h>
18#include <asm/cachetype.h>
19#include <asm/cpu.h>
20#include <asm/cputype.h>
21#include <asm/cpufeature.h>
22
23#include <linux/bitops.h>
24#include <linux/bug.h>
25#include <linux/compat.h>
26#include <linux/elf.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/personality.h>
30#include <linux/preempt.h>
31#include <linux/printk.h>
32#include <linux/seq_file.h>
33#include <linux/sched.h>
34#include <linux/smp.h>
35#include <linux/delay.h>
36
37/*
38 * In case the boot CPU is hotpluggable, we record its initial state and
39 * current state separately. Certain system registers may contain different
40 * values depending on configuration at or after reset.
41 */
42DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
43static struct cpuinfo_arm64 boot_cpu_data;
44
45static char *icache_policy_str[] = {
46	[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
47	[ICACHE_POLICY_AIVIVT] = "AIVIVT",
48	[ICACHE_POLICY_VIPT] = "VIPT",
49	[ICACHE_POLICY_PIPT] = "PIPT",
50};
51
52unsigned long __icache_flags;
53
54static const char *const hwcap_str[] = {
55	"fp",
56	"asimd",
57	"evtstrm",
58	"aes",
59	"pmull",
60	"sha1",
61	"sha2",
62	"crc32",
63	"atomics",
64	NULL
65};
66
67#ifdef CONFIG_COMPAT
68static const char *const compat_hwcap_str[] = {
69	"swp",
70	"half",
71	"thumb",
72	"26bit",
73	"fastmult",
74	"fpa",
75	"vfp",
76	"edsp",
77	"java",
78	"iwmmxt",
79	"crunch",
80	"thumbee",
81	"neon",
82	"vfpv3",
83	"vfpv3d16",
84	"tls",
85	"vfpv4",
86	"idiva",
87	"idivt",
88	"vfpd32",
89	"lpae",
90	"evtstrm",
91	NULL
92};
93
94static const char *const compat_hwcap2_str[] = {
95	"aes",
96	"pmull",
97	"sha1",
98	"sha2",
99	"crc32",
100	NULL
101};
102#endif /* CONFIG_COMPAT */
103
104static int c_show(struct seq_file *m, void *v)
105{
106	int i, j;
107	bool compat = personality(current->personality) == PER_LINUX32;
108
109	for_each_online_cpu(i) {
110		struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
111		u32 midr = cpuinfo->reg_midr;
112
113		/*
114		 * glibc reads /proc/cpuinfo to determine the number of
115		 * online processors, looking for lines beginning with
116		 * "processor".  Give glibc what it expects.
117		 */
118		seq_printf(m, "processor\t: %d\n", i);
119		if (compat)
120			seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
121				   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
122
123		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
124			   loops_per_jiffy / (500000UL/HZ),
125			   loops_per_jiffy / (5000UL/HZ) % 100);
126
127		/*
128		 * Dump out the common processor features in a single line.
129		 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
130		 * rather than attempting to parse this, but there's a body of
131		 * software which does already (at least for 32-bit).
132		 */
133		seq_puts(m, "Features\t:");
134		if (compat) {
135#ifdef CONFIG_COMPAT
136			for (j = 0; compat_hwcap_str[j]; j++)
137				if (compat_elf_hwcap & (1 << j))
138					seq_printf(m, " %s", compat_hwcap_str[j]);
139
140			for (j = 0; compat_hwcap2_str[j]; j++)
141				if (compat_elf_hwcap2 & (1 << j))
142					seq_printf(m, " %s", compat_hwcap2_str[j]);
143#endif /* CONFIG_COMPAT */
144		} else {
145			for (j = 0; hwcap_str[j]; j++)
146				if (elf_hwcap & (1 << j))
147					seq_printf(m, " %s", hwcap_str[j]);
148		}
149		seq_puts(m, "\n");
150
151		seq_printf(m, "CPU implementer\t: 0x%02x\n",
152			   MIDR_IMPLEMENTOR(midr));
153		seq_printf(m, "CPU architecture: 8\n");
154		seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
155		seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
156		seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
157	}
158
159	return 0;
160}
161
162static void *c_start(struct seq_file *m, loff_t *pos)
163{
164	return *pos < 1 ? (void *)1 : NULL;
165}
166
167static void *c_next(struct seq_file *m, void *v, loff_t *pos)
168{
169	++*pos;
170	return NULL;
171}
172
173static void c_stop(struct seq_file *m, void *v)
174{
175}
176
177const struct seq_operations cpuinfo_op = {
178	.start	= c_start,
179	.next	= c_next,
180	.stop	= c_stop,
181	.show	= c_show
182};
183
184static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
185{
186	unsigned int cpu = smp_processor_id();
187	u32 l1ip = CTR_L1IP(info->reg_ctr);
188
189	if (l1ip != ICACHE_POLICY_PIPT) {
190		/*
191		 * VIPT caches are non-aliasing if the VA always equals the PA
192		 * in all bit positions that are covered by the index. This is
193		 * the case if the size of a way (# of sets * line size) does
194		 * not exceed PAGE_SIZE.
195		 */
196		u32 waysize = icache_get_numsets() * icache_get_linesize();
197
198		if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
199			set_bit(ICACHEF_ALIASING, &__icache_flags);
200	}
201	if (l1ip == ICACHE_POLICY_AIVIVT)
202		set_bit(ICACHEF_AIVIVT, &__icache_flags);
203
204	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
205}
206
207static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
208{
209	info->reg_cntfrq = arch_timer_get_cntfrq();
210	info->reg_ctr = read_cpuid_cachetype();
211	info->reg_dczid = read_cpuid(DCZID_EL0);
212	info->reg_midr = read_cpuid_id();
213
214	info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
215	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
216	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
217	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
218	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
219	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
220	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
221	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
222
223	info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
224	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
225	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
226	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
227	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
228	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
229	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
230	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
231	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
232	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
233	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
234	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
235	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
236
237	info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
238	info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
239	info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
240
241	cpuinfo_detect_icache_policy(info);
242
243	check_local_cpu_errata();
244}
245
246void cpuinfo_store_cpu(void)
247{
248	struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
249	__cpuinfo_store_cpu(info);
250	update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
251}
252
253void __init cpuinfo_store_boot_cpu(void)
254{
255	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
256	__cpuinfo_store_cpu(info);
257
258	boot_cpu_data = *info;
259	init_cpu_features(&boot_cpu_data);
260}
261