1/*
2 * Copyright (C) 2010 Google, Inc.
3 *
4 * Author:
5 *	Colin Cross <ccross@google.com>
6 *	Erik Gilling <konkers@google.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef __MACH_TEGRA_IOMAP_H
20#define __MACH_TEGRA_IOMAP_H
21
22#include <asm/pgtable.h>
23#include <asm/sizes.h>
24
25#define TEGRA_IRAM_BASE			0x40000000
26#define TEGRA_IRAM_SIZE			SZ_256K
27
28#define TEGRA_ARM_PERIF_BASE		0x50040000
29#define TEGRA_ARM_PERIF_SIZE		SZ_8K
30
31#define TEGRA_ARM_INT_DIST_BASE		0x50041000
32#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
33
34#define TEGRA_TMR1_BASE			0x60005000
35#define TEGRA_TMR1_SIZE			SZ_8
36
37#define TEGRA_TMR2_BASE			0x60005008
38#define TEGRA_TMR2_SIZE			SZ_8
39
40#define TEGRA_TMRUS_BASE		0x60005010
41#define TEGRA_TMRUS_SIZE		SZ_64
42
43#define TEGRA_TMR3_BASE			0x60005050
44#define TEGRA_TMR3_SIZE			SZ_8
45
46#define TEGRA_TMR4_BASE			0x60005058
47#define TEGRA_TMR4_SIZE			SZ_8
48
49#define TEGRA_CLK_RESET_BASE		0x60006000
50#define TEGRA_CLK_RESET_SIZE		SZ_4K
51
52#define TEGRA_FLOW_CTRL_BASE		0x60007000
53#define TEGRA_FLOW_CTRL_SIZE		20
54
55#define TEGRA_SB_BASE			0x6000C200
56#define TEGRA_SB_SIZE			256
57
58#define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
59#define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
60
61#define TEGRA_APB_MISC_BASE		0x70000000
62#define TEGRA_APB_MISC_SIZE		SZ_4K
63
64#define TEGRA_UARTA_BASE		0x70006000
65#define TEGRA_UARTA_SIZE		SZ_64
66
67#define TEGRA_UARTB_BASE		0x70006040
68#define TEGRA_UARTB_SIZE		SZ_64
69
70#define TEGRA_UARTC_BASE		0x70006200
71#define TEGRA_UARTC_SIZE		SZ_256
72
73#define TEGRA_UARTD_BASE		0x70006300
74#define TEGRA_UARTD_SIZE		SZ_256
75
76#define TEGRA_UARTE_BASE		0x70006400
77#define TEGRA_UARTE_SIZE		SZ_256
78
79#define TEGRA_PMC_BASE			0x7000E400
80#define TEGRA_PMC_SIZE			SZ_256
81
82#define TEGRA_EMC_BASE			0x7000F400
83#define TEGRA_EMC_SIZE			SZ_1K
84
85#define TEGRA_EMC0_BASE			0x7001A000
86#define TEGRA_EMC0_SIZE			SZ_2K
87
88#define TEGRA_EMC1_BASE			0x7001A800
89#define TEGRA_EMC1_SIZE			SZ_2K
90
91#define TEGRA124_EMC_BASE		0x7001B000
92#define TEGRA124_EMC_SIZE		SZ_2K
93
94#define TEGRA_CSITE_BASE		0x70040000
95#define TEGRA_CSITE_SIZE		SZ_256K
96
97/* On TEGRA, many peripherals are very closely packed in
98 * two 256MB io windows (that actually only use about 64KB
99 * at the start of each).
100 *
101 * We will just map the first MMU section of each window (to minimize
102 * pt entries needed) and provide a macro to transform physical
103 * io addresses to an appropriate void __iomem *.
104 */
105
106#define IO_IRAM_PHYS	0x40000000
107#define IO_IRAM_VIRT	IOMEM(0xFE400000)
108#define IO_IRAM_SIZE	SZ_256K
109
110#define IO_CPU_PHYS	0x50040000
111#define IO_CPU_VIRT	IOMEM(0xFE440000)
112#define IO_CPU_SIZE	SZ_16K
113
114#define IO_PPSB_PHYS	0x60000000
115#define IO_PPSB_VIRT	IOMEM(0xFE200000)
116#define IO_PPSB_SIZE	SECTION_SIZE
117
118#define IO_APB_PHYS	0x70000000
119#define IO_APB_VIRT	IOMEM(0xFE000000)
120#define IO_APB_SIZE	SECTION_SIZE
121
122#define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
123#define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
124
125#define IO_TO_VIRT(n) ( \
126	IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?		\
127		IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :	\
128	IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?		\
129		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
130	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
131		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
132	IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ?		\
133		IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) :	\
134	NULL)
135
136#define IO_ADDRESS(n) (IO_TO_VIRT(n))
137
138#endif
139