1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011  Renesas Solutions Corp.
5 * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/irqchip.h>
20#include <linux/irqchip/arm-gic.h>
21#include <linux/of_platform.h>
22
23#include <asm/mach/map.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/time.h>
26#include <asm/hardware/cache-l2x0.h>
27
28#include "common.h"
29
30static struct map_desc r8a7740_io_desc[] __initdata = {
31	 /*
32	  * for CPGA/INTC/PFC
33	  * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
34	  */
35	{
36		.virtual	= 0xe6000000,
37		.pfn		= __phys_to_pfn(0xe6000000),
38		.length		= 160 << 20,
39		.type		= MT_DEVICE_NONSHARED
40	},
41#ifdef CONFIG_CACHE_L2X0
42	/*
43	 * for l2x0_init()
44	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
45	 */
46	{
47		.virtual	= 0xf0002000,
48		.pfn		= __phys_to_pfn(0xf0100000),
49		.length		= PAGE_SIZE,
50		.type		= MT_DEVICE_NONSHARED
51	},
52#endif
53};
54
55static void __init r8a7740_map_io(void)
56{
57	debug_ll_io_init();
58	iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
59}
60
61/*
62 * r8a7740 chip has lasting errata on MERAM buffer.
63 * this is work-around for it.
64 * see
65 *	"Media RAM (MERAM)" on r8a7740 documentation
66 */
67#define MEBUFCNTR	0xFE950098
68static void __init r8a7740_meram_workaround(void)
69{
70	void __iomem *reg;
71
72	reg = ioremap_nocache(MEBUFCNTR, 4);
73	if (reg) {
74		iowrite32(0x01600164, reg);
75		iounmap(reg);
76	}
77}
78
79static void __init r8a7740_init_irq_of(void)
80{
81	void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
82	void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
83	void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
84
85	irqchip_init();
86
87	/* route signals to GIC */
88	iowrite32(0x0, pfc_inta_ctrl);
89
90	/*
91	 * To mask the shared interrupt to SPI 149 we must ensure to set
92	 * PRIO *and* MASK. Else we run into IRQ floods when registering
93	 * the intc_irqpin devices
94	 */
95	iowrite32(0x0, intc_prio_base + 0x0);
96	iowrite32(0x0, intc_prio_base + 0x4);
97	iowrite32(0x0, intc_prio_base + 0x8);
98	iowrite32(0x0, intc_prio_base + 0xc);
99	iowrite8(0xff, intc_msk_base + 0x0);
100	iowrite8(0xff, intc_msk_base + 0x4);
101	iowrite8(0xff, intc_msk_base + 0x8);
102	iowrite8(0xff, intc_msk_base + 0xc);
103
104	iounmap(intc_prio_base);
105	iounmap(intc_msk_base);
106	iounmap(pfc_inta_ctrl);
107}
108
109static void __init r8a7740_generic_init(void)
110{
111	r8a7740_meram_workaround();
112
113#ifdef CONFIG_CACHE_L2X0
114	/* Shared attribute override enable, 32K*8way */
115	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
116#endif
117	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
118}
119
120static const char *const r8a7740_boards_compat_dt[] __initconst = {
121	"renesas,r8a7740",
122	NULL,
123};
124
125DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
126	.map_io		= r8a7740_map_io,
127	.init_early	= shmobile_init_delay,
128	.init_irq	= r8a7740_init_irq_of,
129	.init_machine	= r8a7740_generic_init,
130	.init_late	= shmobile_init_late,
131	.dt_compat	= r8a7740_boards_compat_dt,
132MACHINE_END
133