1/*
2 * OMAP4 PRM instance functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/io.h>
18
19#include "iomap.h"
20#include "common.h"
21#include "prcm-common.h"
22#include "prm44xx.h"
23#include "prm54xx.h"
24#include "prm7xx.h"
25#include "prminst44xx.h"
26#include "prm-regbits-44xx.h"
27#include "prcm44xx.h"
28#include "prcm43xx.h"
29#include "prcm_mpu44xx.h"
30#include "soc.h"
31
32static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
33
34static s32 prm_dev_inst = PRM_INSTANCE_UNKNOWN;
35
36/**
37 * omap_prm_base_init - Populates the prm partitions
38 *
39 * Populates the base addresses of the _prm_bases
40 * array used for read/write of prm module registers.
41 */
42void omap_prm_base_init(void)
43{
44	_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
45	_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
46}
47
48s32 omap4_prmst_get_prm_dev_inst(void)
49{
50	return prm_dev_inst;
51}
52
53void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
54{
55	prm_dev_inst = dev_inst;
56}
57
58/* Read a register in a PRM instance */
59u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
60{
61	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
62	       part == OMAP4430_INVALID_PRCM_PARTITION ||
63	       !_prm_bases[part]);
64	return readl_relaxed(_prm_bases[part] + inst + idx);
65}
66
67/* Write into a register in a PRM instance */
68void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
69{
70	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
71	       part == OMAP4430_INVALID_PRCM_PARTITION ||
72	       !_prm_bases[part]);
73	writel_relaxed(val, _prm_bases[part] + inst + idx);
74}
75
76/* Read-modify-write a register in PRM. Caller must lock */
77u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
78				    u16 idx)
79{
80	u32 v;
81
82	v = omap4_prminst_read_inst_reg(part, inst, idx);
83	v &= ~mask;
84	v |= bits;
85	omap4_prminst_write_inst_reg(v, part, inst, idx);
86
87	return v;
88}
89
90/**
91 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
92 * submodules contained in the hwmod module
93 * @rstctrl_reg: RM_RSTCTRL register address for this module
94 * @shift: register bit shift corresponding to the reset line to check
95 *
96 * Returns 1 if the (sub)module hardreset line is currently asserted,
97 * 0 if the (sub)module hardreset line is not currently asserted, or
98 * -EINVAL upon parameter error.
99 */
100int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
101					u16 rstctrl_offs)
102{
103	u32 v;
104
105	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
106	v &= 1 << shift;
107	v >>= shift;
108
109	return v;
110}
111
112/**
113 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
114 * @rstctrl_reg: RM_RSTCTRL register address for this module
115 * @shift: register bit shift corresponding to the reset line to assert
116 *
117 * Some IPs like dsp, ipu or iva contain processors that require an HW
118 * reset line to be asserted / deasserted in order to fully enable the
119 * IP.  These modules may have multiple hard-reset lines that reset
120 * different 'submodules' inside the IP block.  This function will
121 * place the submodule into reset.  Returns 0 upon success or -EINVAL
122 * upon an argument error.
123 */
124int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
125				   u16 rstctrl_offs)
126{
127	u32 mask = 1 << shift;
128
129	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
130
131	return 0;
132}
133
134/**
135 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
136 * wait
137 * @shift: register bit shift corresponding to the reset line to deassert
138 * @st_shift: status bit offset corresponding to the reset line
139 * @part: PRM partition
140 * @inst: PRM instance offset
141 * @rstctrl_offs: reset register offset
142 * @rstst_offs: reset status register offset
143 *
144 * Some IPs like dsp, ipu or iva contain processors that require an HW
145 * reset line to be asserted / deasserted in order to fully enable the
146 * IP.  These modules may have multiple hard-reset lines that reset
147 * different 'submodules' inside the IP block.  This function will
148 * take the submodule out of reset and wait until the PRCM indicates
149 * that the reset has completed before returning.  Returns 0 upon success or
150 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
151 * of reset, or -EBUSY if the submodule did not exit reset promptly.
152 */
153int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst,
154				     u16 rstctrl_offs, u16 rstst_offs)
155{
156	int c;
157	u32 mask = 1 << shift;
158	u32 st_mask = 1 << st_shift;
159
160	/* Check the current status to avoid de-asserting the line twice */
161	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
162						rstctrl_offs) == 0)
163		return -EEXIST;
164
165	/* Clear the reset status by writing 1 to the status bit */
166	omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst,
167					rstst_offs);
168	/* de-assert the reset control line */
169	omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
170	/* wait the status to be set */
171	omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part,
172							      inst, rstst_offs),
173			  MAX_MODULE_HARDRESET_WAIT, c);
174
175	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
176}
177
178
179void omap4_prminst_global_warm_sw_reset(void)
180{
181	u32 v;
182	s32 inst = omap4_prmst_get_prm_dev_inst();
183
184	if (inst == PRM_INSTANCE_UNKNOWN)
185		return;
186
187	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
188					OMAP4_PRM_RSTCTRL_OFFSET);
189	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
190	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
191				 inst, OMAP4_PRM_RSTCTRL_OFFSET);
192
193	/* OCP barrier */
194	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
195				    inst, OMAP4_PRM_RSTCTRL_OFFSET);
196}
197