1/* 2 * AM33XX PRM functions 3 * 4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/types.h> 18#include <linux/errno.h> 19#include <linux/err.h> 20#include <linux/io.h> 21 22#include "powerdomain.h" 23#include "prm33xx.h" 24#include "prm-regbits-33xx.h" 25 26#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 27 28#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) 29 30/* Read a register in a PRM instance */ 31static u32 am33xx_prm_read_reg(s16 inst, u16 idx) 32{ 33 return readl_relaxed(prm_base + inst + idx); 34} 35 36/* Write into a register in a PRM instance */ 37static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) 38{ 39 writel_relaxed(val, prm_base + inst + idx); 40} 41 42/* Read-modify-write a register in PRM. Caller must lock */ 43static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) 44{ 45 u32 v; 46 47 v = am33xx_prm_read_reg(inst, idx); 48 v &= ~mask; 49 v |= bits; 50 am33xx_prm_write_reg(v, inst, idx); 51 52 return v; 53} 54 55/** 56 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of 57 * submodules contained in the hwmod module 58 * @shift: register bit shift corresponding to the reset line to check 59 * @part: PRM partition, ignored for AM33xx 60 * @inst: CM instance register offset (*_INST macro) 61 * @rstctrl_offs: RM_RSTCTRL register address offset for this module 62 * 63 * Returns 1 if the (sub)module hardreset line is currently asserted, 64 * 0 if the (sub)module hardreset line is not currently asserted, or 65 * -EINVAL upon parameter error. 66 */ 67static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst, 68 u16 rstctrl_offs) 69{ 70 u32 v; 71 72 v = am33xx_prm_read_reg(inst, rstctrl_offs); 73 v &= 1 << shift; 74 v >>= shift; 75 76 return v; 77} 78 79/** 80 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule 81 * @shift: register bit shift corresponding to the reset line to assert 82 * @part: CM partition, ignored for AM33xx 83 * @inst: CM instance register offset (*_INST macro) 84 * @rstctrl_reg: RM_RSTCTRL register address for this module 85 * 86 * Some IPs like dsp, ipu or iva contain processors that require an HW 87 * reset line to be asserted / deasserted in order to fully enable the 88 * IP. These modules may have multiple hard-reset lines that reset 89 * different 'submodules' inside the IP block. This function will 90 * place the submodule into reset. Returns 0 upon success or -EINVAL 91 * upon an argument error. 92 */ 93static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst, 94 u16 rstctrl_offs) 95{ 96 u32 mask = 1 << shift; 97 98 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); 99 100 return 0; 101} 102 103/** 104 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and 105 * wait 106 * @shift: register bit shift corresponding to the reset line to deassert 107 * @st_shift: reset status register bit shift corresponding to the reset line 108 * @part: PRM partition, not used for AM33xx 109 * @inst: CM instance register offset (*_INST macro) 110 * @rstctrl_reg: RM_RSTCTRL register address for this module 111 * @rstst_reg: RM_RSTST register address for this module 112 * 113 * Some IPs like dsp, ipu or iva contain processors that require an HW 114 * reset line to be asserted / deasserted in order to fully enable the 115 * IP. These modules may have multiple hard-reset lines that reset 116 * different 'submodules' inside the IP block. This function will 117 * take the submodule out of reset and wait until the PRCM indicates 118 * that the reset has completed before returning. Returns 0 upon success or 119 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 120 * of reset, or -EBUSY if the submodule did not exit reset promptly. 121 */ 122static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, 123 s16 inst, u16 rstctrl_offs, 124 u16 rstst_offs) 125{ 126 int c; 127 u32 mask = 1 << st_shift; 128 129 /* Check the current status to avoid de-asserting the line twice */ 130 if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0) 131 return -EEXIST; 132 133 /* Clear the reset status by writing 1 to the status bit */ 134 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); 135 136 /* de-assert the reset control line */ 137 mask = 1 << shift; 138 139 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); 140 141 /* wait the status to be set */ 142 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst, 143 rstst_offs), 144 MAX_MODULE_HARDRESET_WAIT, c); 145 146 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 147} 148 149static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) 150{ 151 am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, 152 (pwrst << OMAP_POWERSTATE_SHIFT), 153 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 154 return 0; 155} 156 157static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) 158{ 159 u32 v; 160 161 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 162 v &= OMAP_POWERSTATE_MASK; 163 v >>= OMAP_POWERSTATE_SHIFT; 164 165 return v; 166} 167 168static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) 169{ 170 u32 v; 171 172 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 173 v &= OMAP_POWERSTATEST_MASK; 174 v >>= OMAP_POWERSTATEST_SHIFT; 175 176 return v; 177} 178 179static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) 180{ 181 u32 v; 182 183 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 184 v &= AM33XX_LASTPOWERSTATEENTERED_MASK; 185 v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; 186 187 return v; 188} 189 190static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) 191{ 192 am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, 193 (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), 194 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 195 return 0; 196} 197 198static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) 199{ 200 am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, 201 AM33XX_LASTPOWERSTATEENTERED_MASK, 202 pwrdm->prcm_offs, pwrdm->pwrstst_offs); 203 return 0; 204} 205 206static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 207{ 208 u32 m; 209 210 m = pwrdm->logicretstate_mask; 211 if (!m) 212 return -EINVAL; 213 214 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), 215 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 216 217 return 0; 218} 219 220static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) 221{ 222 u32 v; 223 224 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 225 v &= AM33XX_LOGICSTATEST_MASK; 226 v >>= AM33XX_LOGICSTATEST_SHIFT; 227 228 return v; 229} 230 231static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) 232{ 233 u32 v, m; 234 235 m = pwrdm->logicretstate_mask; 236 if (!m) 237 return -EINVAL; 238 239 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 240 v &= m; 241 v >>= __ffs(m); 242 243 return v; 244} 245 246static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, 247 u8 pwrst) 248{ 249 u32 m; 250 251 m = pwrdm->mem_on_mask[bank]; 252 if (!m) 253 return -EINVAL; 254 255 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), 256 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 257 258 return 0; 259} 260 261static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, 262 u8 pwrst) 263{ 264 u32 m; 265 266 m = pwrdm->mem_ret_mask[bank]; 267 if (!m) 268 return -EINVAL; 269 270 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), 271 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 272 273 return 0; 274} 275 276static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) 277{ 278 u32 m, v; 279 280 m = pwrdm->mem_pwrst_mask[bank]; 281 if (!m) 282 return -EINVAL; 283 284 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); 285 v &= m; 286 v >>= __ffs(m); 287 288 return v; 289} 290 291static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) 292{ 293 u32 m, v; 294 295 m = pwrdm->mem_retst_mask[bank]; 296 if (!m) 297 return -EINVAL; 298 299 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); 300 v &= m; 301 v >>= __ffs(m); 302 303 return v; 304} 305 306static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) 307{ 308 u32 c = 0; 309 310 /* 311 * REVISIT: pwrdm_wait_transition() may be better implemented 312 * via a callback and a periodic timer check -- how long do we expect 313 * powerdomain transitions to take? 314 */ 315 316 /* XXX Is this udelay() value meaningful? */ 317 while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) 318 & OMAP_INTRANSITION_MASK) && 319 (c++ < PWRDM_TRANSITION_BAILOUT)) 320 udelay(1); 321 322 if (c > PWRDM_TRANSITION_BAILOUT) { 323 pr_err("powerdomain: %s: waited too long to complete transition\n", 324 pwrdm->name); 325 return -EAGAIN; 326 } 327 328 pr_debug("powerdomain: completed transition in %d loops\n", c); 329 330 return 0; 331} 332 333static int am33xx_check_vcvp(void) 334{ 335 /* No VC/VP on am33xx devices */ 336 return 0; 337} 338 339/** 340 * am33xx_prm_global_warm_sw_reset - reboot the device via warm reset 341 * 342 * Immediately reboots the device through warm reset. 343 */ 344static void am33xx_prm_global_warm_sw_reset(void) 345{ 346 am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, 347 AM33XX_RST_GLOBAL_WARM_SW_MASK, 348 AM33XX_PRM_DEVICE_MOD, 349 AM33XX_PRM_RSTCTRL_OFFSET); 350 351 /* OCP barrier */ 352 (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD, 353 AM33XX_PRM_RSTCTRL_OFFSET); 354} 355 356struct pwrdm_ops am33xx_pwrdm_operations = { 357 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, 358 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, 359 .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, 360 .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, 361 .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, 362 .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, 363 .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, 364 .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, 365 .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, 366 .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, 367 .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, 368 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, 369 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, 370 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, 371 .pwrdm_has_voltdm = am33xx_check_vcvp, 372}; 373 374static struct prm_ll_data am33xx_prm_ll_data = { 375 .assert_hardreset = am33xx_prm_assert_hardreset, 376 .deassert_hardreset = am33xx_prm_deassert_hardreset, 377 .is_hardreset_asserted = am33xx_prm_is_hardreset_asserted, 378 .reset_system = am33xx_prm_global_warm_sw_reset, 379}; 380 381int __init am33xx_prm_init(const struct omap_prcm_init_data *data) 382{ 383 return prm_register(&am33xx_prm_ll_data); 384} 385 386static void __exit am33xx_prm_exit(void) 387{ 388 prm_unregister(&am33xx_prm_ll_data); 389} 390__exitcall(am33xx_prm_exit); 391