1/*
2 * AM33XX Power domain data
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include "powerdomain.h"
20#include "prcm-common.h"
21#include "prm-regbits-33xx.h"
22#include "prm33xx.h"
23
24static struct powerdomain gfx_33xx_pwrdm = {
25	.name			= "gfx_pwrdm",
26	.voltdm			= { .name = "core" },
27	.prcm_offs		= AM33XX_PRM_GFX_MOD,
28	.pwrstctrl_offs		= AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
29	.pwrstst_offs		= AM33XX_PM_GFX_PWRSTST_OFFSET,
30	.pwrsts			= PWRSTS_OFF_RET_ON,
31	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
32	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
33	.banks			= 1,
34	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
35	.mem_on_mask		= {
36		[0]		= AM33XX_GFX_MEM_ONSTATE_MASK,	/* gfx_mem */
37	},
38	.mem_ret_mask		= {
39		[0]		= AM33XX_GFX_MEM_RETSTATE_MASK,	/* gfx_mem */
40	},
41	.mem_pwrst_mask		= {
42		[0]		= AM33XX_GFX_MEM_STATEST_MASK,	/* gfx_mem */
43	},
44	.mem_retst_mask		= {
45		[0]		= AM33XX_GFX_MEM_RETSTATE_MASK,	/* gfx_mem */
46	},
47	.pwrsts_mem_ret		= {
48		[0]		= PWRSTS_OFF_RET,	/* gfx_mem */
49	},
50	.pwrsts_mem_on		= {
51		[0]		= PWRSTS_ON,		/* gfx_mem */
52	},
53};
54
55static struct powerdomain rtc_33xx_pwrdm = {
56	.name			= "rtc_pwrdm",
57	.voltdm			= { .name = "rtc" },
58	.prcm_offs		= AM33XX_PRM_RTC_MOD,
59	.pwrstctrl_offs		= AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
60	.pwrstst_offs		= AM33XX_PM_RTC_PWRSTST_OFFSET,
61	.pwrsts			= PWRSTS_ON,
62	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
63};
64
65static struct powerdomain wkup_33xx_pwrdm = {
66	.name			= "wkup_pwrdm",
67	.voltdm			= { .name = "core" },
68	.prcm_offs		= AM33XX_PRM_WKUP_MOD,
69	.pwrstctrl_offs		= AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
70	.pwrstst_offs		= AM33XX_PM_WKUP_PWRSTST_OFFSET,
71	.pwrsts			= PWRSTS_ON,
72	.logicretstate_mask	= AM33XX_LOGICRETSTATE_3_3_MASK,
73};
74
75static struct powerdomain per_33xx_pwrdm = {
76	.name			= "per_pwrdm",
77	.voltdm			= { .name = "core" },
78	.prcm_offs		= AM33XX_PRM_PER_MOD,
79	.pwrstctrl_offs		= AM33XX_PM_PER_PWRSTCTRL_OFFSET,
80	.pwrstst_offs		= AM33XX_PM_PER_PWRSTST_OFFSET,
81	.pwrsts			= PWRSTS_OFF_RET_ON,
82	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
83	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
84	.banks			= 3,
85	.logicretstate_mask	= AM33XX_LOGICRETSTATE_3_3_MASK,
86	.mem_on_mask		= {
87		[0]		= AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
88		[1]		= AM33XX_PER_MEM_ONSTATE_MASK,	/* per_mem */
89		[2]		= AM33XX_RAM_MEM_ONSTATE_MASK,	/* ram_mem */
90	},
91	.mem_ret_mask		= {
92		[0]		= AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
93		[1]		= AM33XX_PER_MEM_RETSTATE_MASK,	/* per_mem */
94		[2]		= AM33XX_RAM_MEM_RETSTATE_MASK,	/* ram_mem */
95	},
96	.mem_pwrst_mask		= {
97		[0]		= AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
98		[1]		= AM33XX_PER_MEM_STATEST_MASK,	/* per_mem */
99		[2]		= AM33XX_RAM_MEM_STATEST_MASK,	/* ram_mem */
100	},
101	.mem_retst_mask		= {
102		[0]		= AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
103		[1]		= AM33XX_PER_MEM_RETSTATE_MASK,	/* per_mem */
104		[2]		= AM33XX_RAM_MEM_RETSTATE_MASK,	/* ram_mem */
105	},
106	.pwrsts_mem_ret		= {
107		[0]		= PWRSTS_OFF_RET,	/* pruss_mem */
108		[1]		= PWRSTS_OFF_RET,	/* per_mem */
109		[2]		= PWRSTS_OFF_RET,	/* ram_mem */
110	},
111	.pwrsts_mem_on		= {
112		[0]		= PWRSTS_ON,		/* pruss_mem */
113		[1]		= PWRSTS_ON,		/* per_mem */
114		[2]		= PWRSTS_ON,		/* ram_mem */
115	},
116};
117
118static struct powerdomain mpu_33xx_pwrdm = {
119	.name			= "mpu_pwrdm",
120	.voltdm			= { .name = "mpu" },
121	.prcm_offs		= AM33XX_PRM_MPU_MOD,
122	.pwrstctrl_offs		= AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
123	.pwrstst_offs		= AM33XX_PM_MPU_PWRSTST_OFFSET,
124	.pwrsts			= PWRSTS_OFF_RET_ON,
125	.pwrsts_logic_ret	= PWRSTS_OFF_RET,
126	.flags			= PWRDM_HAS_LOWPOWERSTATECHANGE,
127	.banks			= 3,
128	.logicretstate_mask	= AM33XX_LOGICRETSTATE_MASK,
129	.mem_on_mask		= {
130		[0]		= AM33XX_MPU_L1_ONSTATE_MASK,	/* mpu_l1 */
131		[1]		= AM33XX_MPU_L2_ONSTATE_MASK,	/* mpu_l2 */
132		[2]		= AM33XX_MPU_RAM_ONSTATE_MASK,	/* mpu_ram */
133	},
134	.mem_ret_mask		= {
135		[0]		= AM33XX_MPU_L1_RETSTATE_MASK,	/* mpu_l1 */
136		[1]		= AM33XX_MPU_L2_RETSTATE_MASK,	/* mpu_l2 */
137		[2]		= AM33XX_MPU_RAM_RETSTATE_MASK,	/* mpu_ram */
138	},
139	.mem_pwrst_mask		= {
140		[0]		= AM33XX_MPU_L1_STATEST_MASK,	/* mpu_l1 */
141		[1]		= AM33XX_MPU_L2_STATEST_MASK,	/* mpu_l2 */
142		[2]		= AM33XX_MPU_RAM_STATEST_MASK,	/* mpu_ram */
143	},
144	.mem_retst_mask		= {
145		[0]		= AM33XX_MPU_L1_RETSTATE_MASK,	/* mpu_l1 */
146		[1]		= AM33XX_MPU_L2_RETSTATE_MASK,	/* mpu_l2 */
147		[2]		= AM33XX_MPU_RAM_RETSTATE_MASK,	/* mpu_ram */
148	},
149	.pwrsts_mem_ret		= {
150		[0]		= PWRSTS_OFF_RET,	/* mpu_l1 */
151		[1]		= PWRSTS_OFF_RET,	/* mpu_l2 */
152		[2]		= PWRSTS_OFF_RET,	/* mpu_ram */
153	},
154	.pwrsts_mem_on		= {
155		[0]		= PWRSTS_ON,		/* mpu_l1 */
156		[1]		= PWRSTS_ON,		/* mpu_l2 */
157		[2]		= PWRSTS_ON,		/* mpu_ram */
158	},
159};
160
161static struct powerdomain cefuse_33xx_pwrdm = {
162	.name		= "cefuse_pwrdm",
163	.voltdm		= { .name = "core" },
164	.prcm_offs	= AM33XX_PRM_CEFUSE_MOD,
165	.pwrstctrl_offs	= AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
166	.pwrstst_offs	= AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
167	.pwrsts		= PWRSTS_OFF_ON,
168};
169
170static struct powerdomain *powerdomains_am33xx[] __initdata = {
171	&gfx_33xx_pwrdm,
172	&rtc_33xx_pwrdm,
173	&wkup_33xx_pwrdm,
174	&per_33xx_pwrdm,
175	&mpu_33xx_pwrdm,
176	&cefuse_33xx_pwrdm,
177	NULL,
178};
179
180void __init am33xx_powerdomains_init(void)
181{
182	pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
183	pwrdm_register_pwrdms(powerdomains_am33xx);
184	pwrdm_complete_init();
185}
186