1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
3
4/*
5 * OMAP24XX Clock Management register bits
6 *
7 * Copyright (C) 2007 Texas Instruments, Inc.
8 * Copyright (C) 2007 Nokia Corporation
9 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#define OMAP24XX_EN_CAM_SHIFT				31
18#define OMAP24XX_EN_WDT4_SHIFT				29
19#define OMAP2420_EN_WDT3_SHIFT				28
20#define OMAP24XX_EN_MSPRO_SHIFT				27
21#define OMAP24XX_EN_FAC_SHIFT				25
22#define OMAP2420_EN_EAC_SHIFT				24
23#define OMAP24XX_EN_HDQ_SHIFT				23
24#define OMAP2420_EN_I2C2_SHIFT				20
25#define OMAP2420_EN_I2C1_SHIFT				19
26#define OMAP2430_EN_MCBSP5_SHIFT			5
27#define OMAP2430_EN_MCBSP4_SHIFT			4
28#define OMAP2430_EN_MCBSP3_SHIFT			3
29#define OMAP24XX_EN_SSI_SHIFT				1
30#define OMAP24XX_EN_MPU_WDT_SHIFT			3
31#define OMAP24XX_CLKSEL_MPU_SHIFT			0
32#define OMAP24XX_CLKSEL_MPU_WIDTH			5
33#define OMAP24XX_AUTOSTATE_MPU_MASK			(1 << 0)
34#define OMAP24XX_EN_TV_SHIFT				2
35#define OMAP24XX_EN_DSS2_SHIFT				1
36#define OMAP24XX_EN_DSS1_SHIFT				0
37#define OMAP24XX_EN_DSS1_MASK				(1 << 0)
38#define OMAP2430_EN_I2CHS2_SHIFT			20
39#define OMAP2430_EN_I2CHS1_SHIFT			19
40#define OMAP2430_EN_MMCHSDB2_SHIFT			17
41#define OMAP2430_EN_MMCHSDB1_SHIFT			16
42#define OMAP24XX_EN_MAILBOXES_SHIFT			30
43#define OMAP2430_EN_SDRC_SHIFT				2
44#define OMAP24XX_EN_PKA_SHIFT				4
45#define OMAP24XX_EN_AES_SHIFT				3
46#define OMAP24XX_EN_RNG_SHIFT				2
47#define OMAP24XX_EN_SHA_SHIFT				1
48#define OMAP24XX_EN_DES_SHIFT				0
49#define OMAP24XX_ST_MAILBOXES_SHIFT			30
50#define OMAP24XX_ST_HDQ_SHIFT				23
51#define OMAP2420_ST_I2C2_SHIFT				20
52#define OMAP2430_ST_I2CHS1_SHIFT			19
53#define OMAP2420_ST_I2C1_SHIFT				19
54#define OMAP2430_ST_I2CHS2_SHIFT			20
55#define OMAP24XX_ST_MCBSP2_SHIFT			16
56#define OMAP24XX_ST_MCBSP1_SHIFT			15
57#define OMAP24XX_ST_DSS_SHIFT				0
58#define OMAP2430_ST_MCBSP5_SHIFT			5
59#define OMAP2430_ST_MCBSP4_SHIFT			4
60#define OMAP2430_ST_MCBSP3_SHIFT			3
61#define OMAP24XX_ST_AES_SHIFT				3
62#define OMAP24XX_ST_RNG_SHIFT				2
63#define OMAP24XX_ST_SHA_SHIFT				1
64#define OMAP24XX_AUTO_SDRC_SHIFT			2
65#define OMAP24XX_AUTO_GPMC_SHIFT			1
66#define OMAP24XX_AUTO_SDMA_SHIFT			0
67#define OMAP24XX_CLKSEL_USB_MASK			(0x7 << 25)
68#define OMAP24XX_CLKSEL_SSI_MASK			(0x1f << 20)
69#define OMAP2420_CLKSEL_VLYNQ_MASK			(0x1f << 15)
70#define OMAP24XX_CLKSEL_DSS2_MASK			(0x1 << 13)
71#define OMAP24XX_CLKSEL_DSS1_MASK			(0x1f << 8)
72#define OMAP24XX_CLKSEL_L4_SHIFT			5
73#define OMAP24XX_CLKSEL_L4_WIDTH			2
74#define OMAP24XX_CLKSEL_L3_SHIFT			0
75#define OMAP24XX_CLKSEL_L3_WIDTH			5
76#define OMAP24XX_CLKSEL_GPT12_MASK			(0x3 << 22)
77#define OMAP24XX_CLKSEL_GPT11_MASK			(0x3 << 20)
78#define OMAP24XX_CLKSEL_GPT10_MASK			(0x3 << 18)
79#define OMAP24XX_CLKSEL_GPT9_MASK			(0x3 << 16)
80#define OMAP24XX_CLKSEL_GPT8_MASK			(0x3 << 14)
81#define OMAP24XX_CLKSEL_GPT7_MASK			(0x3 << 12)
82#define OMAP24XX_CLKSEL_GPT6_MASK			(0x3 << 10)
83#define OMAP24XX_CLKSEL_GPT5_MASK			(0x3 << 8)
84#define OMAP24XX_CLKSEL_GPT4_MASK			(0x3 << 6)
85#define OMAP24XX_CLKSEL_GPT3_MASK			(0x3 << 4)
86#define OMAP24XX_CLKSEL_GPT2_MASK			(0x3 << 2)
87#define OMAP24XX_AUTOSTATE_DSS_MASK			(1 << 2)
88#define OMAP24XX_AUTOSTATE_L4_MASK			(1 << 1)
89#define OMAP24XX_AUTOSTATE_L3_MASK			(1 << 0)
90#define OMAP24XX_EN_3D_SHIFT				2
91#define OMAP24XX_EN_2D_SHIFT				1
92#define OMAP24XX_AUTOSTATE_GFX_MASK			(1 << 0)
93#define OMAP2430_EN_ICR_SHIFT				6
94#define OMAP24XX_EN_OMAPCTRL_SHIFT			5
95#define OMAP24XX_EN_WDT1_SHIFT				4
96#define OMAP24XX_EN_32KSYNC_SHIFT			1
97#define OMAP24XX_ST_MPU_WDT_SHIFT			3
98#define OMAP24XX_ST_32KSYNC_SHIFT			1
99#define OMAP24XX_CLKSEL_GPT1_MASK			(0x3 << 0)
100#define OMAP24XX_EN_54M_PLL_SHIFT			6
101#define OMAP24XX_EN_96M_PLL_SHIFT			2
102#define OMAP24XX_EN_DPLL_MASK				(0x3 << 0)
103#define OMAP24XX_ST_54M_APLL_SHIFT			9
104#define OMAP24XX_ST_96M_APLL_SHIFT			8
105#define OMAP24XX_AUTO_54M_MASK				(0x3 << 6)
106#define OMAP24XX_AUTO_96M_MASK				(0x3 << 2)
107#define OMAP24XX_AUTO_DPLL_SHIFT			0
108#define OMAP24XX_AUTO_DPLL_MASK				(0x3 << 0)
109#define OMAP24XX_APLLS_CLKIN_SHIFT			23
110#define OMAP24XX_APLLS_CLKIN_WIDTH			3
111#define OMAP24XX_APLLS_CLKIN_MASK			(0x7 << 23)
112#define OMAP24XX_DPLL_MULT_MASK				(0x3ff << 12)
113#define OMAP24XX_DPLL_DIV_MASK				(0xf << 8)
114#define OMAP24XX_54M_SOURCE_SHIFT			5
115#define OMAP24XX_54M_SOURCE_WIDTH			1
116#define OMAP2430_96M_SOURCE_SHIFT			4
117#define OMAP2430_96M_SOURCE_WIDTH			1
118#define OMAP24XX_48M_SOURCE_MASK			(1 << 3)
119#define OMAP24XX_CORE_CLK_SRC_MASK			(0x3 << 0)
120#define OMAP2420_EN_IVA_COP_SHIFT			10
121#define OMAP2420_EN_IVA_MPU_SHIFT			8
122#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT		0
123#define OMAP2420_EN_DSP_IPI_SHIFT			1
124#define OMAP2420_CLKSEL_IVA_MASK			(0x1f << 8)
125#define OMAP24XX_CLKSEL_DSP_IF_MASK			(0x3 << 5)
126#define OMAP24XX_CLKSEL_DSP_MASK			(0x1f << 0)
127#define OMAP2420_AUTOSTATE_IVA_MASK			(1 << 8)
128#define OMAP24XX_AUTOSTATE_DSP_MASK			(1 << 0)
129#define OMAP2430_EN_OSC_SHIFT				1
130#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT		0
131#define OMAP2430_CLKSEL_MDM_MASK			(0xf << 0)
132#define OMAP2430_AUTOSTATE_MDM_MASK			(1 << 0)
133#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO		0x0
134#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO		0x1
135#endif
136