1/*
2 * DPLL + CORE_CLK composite clock functions
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * XXX The DPLL and CORE clocks should be split into two separate clock
19 * types.
20 */
21#undef DEBUG
22
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27
28#include "clock.h"
29#include "clock2xxx.h"
30#include "opp2xxx.h"
31#include "cm2xxx.h"
32#include "cm-regbits-24xx.h"
33#include "sdrc.h"
34#include "sram.h"
35
36/* #define DOWN_VARIABLE_DPLL 1 */		/* Experimental */
37
38/*
39 * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
40 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
41 * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
42 */
43static struct clk_hw_omap *dpll_core_ck;
44
45/**
46 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
47 *
48 * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
49 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
50 * (the latter is unusual).  This currently should be called with
51 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
52 * core_ck.
53 */
54unsigned long omap2xxx_clk_get_core_rate(void)
55{
56	long long core_clk;
57	u32 v;
58
59	WARN_ON(!dpll_core_ck);
60
61	core_clk = omap2_get_dpll_rate(dpll_core_ck);
62
63	v = omap2xxx_cm_get_core_clk_src();
64
65	if (v == CORE_CLK_SRC_32K)
66		core_clk = 32768;
67	else
68		core_clk *= v;
69
70	return core_clk;
71}
72
73/*
74 * Uses the current prcm set to tell if a rate is valid.
75 * You can go slower, but not faster within a given rate set.
76 */
77static long omap2_dpllcore_round_rate(unsigned long target_rate)
78{
79	u32 high, low, core_clk_src;
80
81	core_clk_src = omap2xxx_cm_get_core_clk_src();
82
83	if (core_clk_src == CORE_CLK_SRC_DPLL) {	/* DPLL clockout */
84		high = curr_prcm_set->dpll_speed * 2;
85		low = curr_prcm_set->dpll_speed;
86	} else {				/* DPLL clockout x 2 */
87		high = curr_prcm_set->dpll_speed;
88		low = curr_prcm_set->dpll_speed / 2;
89	}
90
91#ifdef DOWN_VARIABLE_DPLL
92	if (target_rate > high)
93		return high;
94	else
95		return target_rate;
96#else
97	if (target_rate > low)
98		return high;
99	else
100		return low;
101#endif
102
103}
104
105unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
106				    unsigned long parent_rate)
107{
108	return omap2xxx_clk_get_core_rate();
109}
110
111int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
112			     unsigned long parent_rate)
113{
114	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
115	u32 cur_rate, low, mult, div, valid_rate, done_rate;
116	u32 bypass = 0;
117	struct prcm_config tmpset;
118	const struct dpll_data *dd;
119
120	cur_rate = omap2xxx_clk_get_core_rate();
121	mult = omap2xxx_cm_get_core_clk_src();
122
123	if ((rate == (cur_rate / 2)) && (mult == 2)) {
124		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
125	} else if ((rate == (cur_rate * 2)) && (mult == 1)) {
126		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
127	} else if (rate != cur_rate) {
128		valid_rate = omap2_dpllcore_round_rate(rate);
129		if (valid_rate != rate)
130			return -EINVAL;
131
132		if (mult == 1)
133			low = curr_prcm_set->dpll_speed;
134		else
135			low = curr_prcm_set->dpll_speed / 2;
136
137		dd = clk->dpll_data;
138		if (!dd)
139			return -EINVAL;
140
141		tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);
142		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
143					   dd->div1_mask);
144		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
145		tmpset.cm_clksel2_pll = omap2xxx_cm_get_core_pll_config();
146		tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
147		if (rate > low) {
148			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
149			mult = ((rate / 2) / 1000000);
150			done_rate = CORE_CLK_SRC_DPLL_X2;
151		} else {
152			tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
153			mult = (rate / 1000000);
154			done_rate = CORE_CLK_SRC_DPLL;
155		}
156		tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
157		tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
158
159		/* Worst case */
160		tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
161
162		if (rate == curr_prcm_set->xtal_speed)	/* If asking for 1-1 */
163			bypass = 1;
164
165		/* For omap2xxx_sdrc_init_params() */
166		omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
167
168		/* Force dll lock mode */
169		omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
170			       bypass);
171
172		/* Errata: ret dll entry state */
173		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
174		omap2xxx_sdrc_reprogram(done_rate, 0);
175	}
176
177	return 0;
178}
179
180/**
181 * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
182 * @clk: struct clk *dpll_ck
183 *
184 * Store a local copy of @clk in dpll_core_ck so other code can query
185 * the core rate without having to clk_get(), which can sleep.  Must
186 * only be called once.  No return value.  XXX If the clock
187 * registration process is ever changed such that dpll_ck is no longer
188 * statically defined, this code may need to change to increment some
189 * kind of use count on dpll_ck.
190 */
191void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
192{
193	WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
194	dpll_core_ck = to_clk_hw_omap(hw);
195}
196