1/*
2 * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
3 *
4 * Generic definitions for Marvell MV78xx0 SoC flavors:
5 *  MV781x0 and MV782x0.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2.  This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_MV78XX0_H
13#define __ASM_ARCH_MV78XX0_H
14
15/*
16 * Marvell MV78xx0 address maps.
17 *
18 * phys
19 * c0000000	PCIe Memory space
20 * f0800000	PCIe #0 I/O space
21 * f0900000	PCIe #1 I/O space
22 * f0a00000	PCIe #2 I/O space
23 * f0b00000	PCIe #3 I/O space
24 * f0c00000	PCIe #4 I/O space
25 * f0d00000	PCIe #5 I/O space
26 * f0e00000	PCIe #6 I/O space
27 * f0f00000	PCIe #7 I/O space
28 * f1000000	on-chip peripheral registers
29 *
30 * virt		phys		size
31 * fe400000	f102x000	16K	core-specific peripheral registers
32 * fee00000	f0800000	64K	PCIe #0 I/O space
33 * fee10000	f0900000	64K	PCIe #1 I/O space
34 * fee20000	f0a00000	64K	PCIe #2 I/O space
35 * fee30000	f0b00000	64K	PCIe #3 I/O space
36 * fee40000	f0c00000	64K	PCIe #4 I/O space
37 * fee50000	f0d00000	64K	PCIe #5 I/O space
38 * fee60000	f0e00000	64K	PCIe #6 I/O space
39 * fee70000	f0f00000	64K	PCIe #7 I/O space
40 * fd000000	f1000000	1M	on-chip peripheral registers
41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE	0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE	0xf1024000
44#define MV78XX0_CORE_REGS_VIRT_BASE	IOMEM(0xfe400000)
45#define MV78XX0_CORE_REGS_PHYS_BASE	0xfe400000
46#define MV78XX0_CORE_REGS_SIZE		SZ_16K
47
48#define MV78XX0_PCIE_IO_PHYS_BASE(i)	(0xf0800000 + ((i) << 20))
49#define MV78XX0_PCIE_IO_SIZE		SZ_1M
50
51#define MV78XX0_REGS_PHYS_BASE		0xf1000000
52#define MV78XX0_REGS_VIRT_BASE		IOMEM(0xfd000000)
53#define MV78XX0_REGS_SIZE		SZ_1M
54
55#define MV78XX0_PCIE_MEM_PHYS_BASE	0xc0000000
56#define MV78XX0_PCIE_MEM_SIZE		0x30000000
57
58/*
59 * Core-specific peripheral registers.
60 */
61#define BRIDGE_VIRT_BASE	(MV78XX0_CORE_REGS_VIRT_BASE)
62#define BRIDGE_PHYS_BASE	(MV78XX0_CORE_REGS_PHYS_BASE)
63#define  BRIDGE_WINS_CPU0_BASE  (MV78XX0_CORE0_REGS_PHYS_BASE)
64#define  BRIDGE_WINS_CPU1_BASE  (MV78XX0_CORE1_REGS_PHYS_BASE)
65#define  BRIDGE_WINS_SZ         (0xA000)
66
67/*
68 * Register Map
69 */
70#define DDR_VIRT_BASE		(MV78XX0_REGS_VIRT_BASE + 0x00000)
71#define DDR_PHYS_BASE           (MV78XX0_REGS_PHYS_BASE + 0x00000)
72#define  DDR_WINDOW_CPU0_BASE	(DDR_PHYS_BASE + 0x1500)
73#define  DDR_WINDOW_CPU1_BASE	(DDR_PHYS_BASE + 0x1570)
74#define  DDR_WINDOW_CPU_SZ      (0x20)
75
76#define DEV_BUS_PHYS_BASE	(MV78XX0_REGS_PHYS_BASE + 0x10000)
77#define DEV_BUS_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x10000)
78#define  SAMPLE_AT_RESET_LOW	(DEV_BUS_VIRT_BASE + 0x0030)
79#define  SAMPLE_AT_RESET_HIGH	(DEV_BUS_VIRT_BASE + 0x0034)
80#define  GPIO_VIRT_BASE		(DEV_BUS_VIRT_BASE + 0x0100)
81#define  I2C_0_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x1000)
82#define  I2C_1_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x1100)
83#define  UART0_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2000)
84#define  UART0_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2000)
85#define  UART1_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2100)
86#define  UART1_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2100)
87#define  UART2_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2200)
88#define  UART2_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2200)
89#define  UART3_PHYS_BASE	(DEV_BUS_PHYS_BASE + 0x2300)
90#define  UART3_VIRT_BASE	(DEV_BUS_VIRT_BASE + 0x2300)
91
92#define GE10_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x30000)
93#define GE11_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x34000)
94
95#define PCIE00_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x40000)
96#define PCIE01_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x44000)
97#define PCIE02_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x48000)
98#define PCIE03_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x4c000)
99
100#define USB0_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x50000)
101#define USB1_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x51000)
102#define USB2_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x52000)
103
104#define GE00_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x70000)
105#define GE01_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0x74000)
106
107#define PCIE10_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x80000)
108#define PCIE11_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x84000)
109#define PCIE12_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x88000)
110#define PCIE13_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x8c000)
111
112#define SATA_PHYS_BASE		(MV78XX0_REGS_PHYS_BASE + 0xa0000)
113
114/*
115 * Supported devices and revisions.
116 */
117#define MV78X00_Z0_DEV_ID	0x6381
118#define MV78X00_REV_Z0		1
119
120#define MV78100_DEV_ID		0x7810
121#define MV78100_REV_A0		1
122#define MV78100_REV_A1		2
123
124#define MV78200_DEV_ID		0x7820
125#define MV78200_REV_A0		1
126
127#endif
128