1/*
2 * linux/arch/arm/mach-mmp/include/mach/regs-icu.h
3 *
4 *   Interrupt Control Unit
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ICU_H
12#define __ASM_MACH_ICU_H
13
14#include <mach/addr-map.h>
15
16#define ICU_VIRT_BASE	(AXI_VIRT_BASE + 0x82000)
17#define ICU_REG(x)	(ICU_VIRT_BASE + (x))
18
19#define ICU_INT_CONF(n)		ICU_REG((n) << 2)
20#define ICU_INT_CONF_MASK	(0xf)
21
22/************ PXA168/PXA910 (MMP) *********************/
23#define ICU_INT_CONF_AP_INT	(1 << 6)
24#define ICU_INT_CONF_CP_INT	(1 << 5)
25#define ICU_INT_CONF_IRQ	(1 << 4)
26
27#define ICU_AP_FIQ_SEL_INT_NUM	ICU_REG(0x108)	/* AP FIQ Selected Interrupt */
28#define ICU_AP_IRQ_SEL_INT_NUM	ICU_REG(0x10C)	/* AP IRQ Selected Interrupt */
29#define ICU_AP_GBL_IRQ_MSK	ICU_REG(0x114)	/* AP Global Interrupt Mask */
30#define ICU_INT_STATUS_0	ICU_REG(0x128)	/* Interrupt Stuats 0 */
31#define ICU_INT_STATUS_1	ICU_REG(0x12C)	/* Interrupt Status 1 */
32
33/************************** MMP2 ***********************/
34
35/*
36 * IRQ0/FIQ0 is routed to SP IRQ/FIQ.
37 * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ.
38 */
39#define ICU_INT_ROUTE_SP_IRQ		(1 << 4)
40#define ICU_INT_ROUTE_PJ4_IRQ		(1 << 5)
41#define ICU_INT_ROUTE_PJ4_FIQ		(1 << 6)
42
43#define MMP2_ICU_PJ4_IRQ_STATUS0	ICU_REG(0x138)
44#define MMP2_ICU_PJ4_IRQ_STATUS1	ICU_REG(0x13c)
45#define MMP2_ICU_PJ4_FIQ_STATUS0	ICU_REG(0x140)
46#define MMP2_ICU_PJ4_FIQ_STATUS1	ICU_REG(0x144)
47
48#define MMP2_ICU_INT4_STATUS		ICU_REG(0x150)
49#define MMP2_ICU_INT5_STATUS		ICU_REG(0x154)
50#define MMP2_ICU_INT17_STATUS		ICU_REG(0x158)
51#define MMP2_ICU_INT35_STATUS		ICU_REG(0x15c)
52#define MMP2_ICU_INT51_STATUS		ICU_REG(0x160)
53
54#define MMP2_ICU_INT4_MASK		ICU_REG(0x168)
55#define MMP2_ICU_INT5_MASK		ICU_REG(0x16C)
56#define MMP2_ICU_INT17_MASK		ICU_REG(0x170)
57#define MMP2_ICU_INT35_MASK		ICU_REG(0x174)
58#define MMP2_ICU_INT51_MASK		ICU_REG(0x178)
59
60#define MMP2_ICU_SP_IRQ_SEL		ICU_REG(0x100)
61#define MMP2_ICU_PJ4_IRQ_SEL		ICU_REG(0x104)
62#define MMP2_ICU_PJ4_FIQ_SEL		ICU_REG(0x108)
63
64#define MMP2_ICU_INVERT			ICU_REG(0x164)
65
66#define MMP2_ICU_INV_PMIC		(1 << 0)
67#define MMP2_ICU_INV_PERF		(1 << 1)
68#define MMP2_ICU_INV_COMMTX		(1 << 2)
69#define MMP2_ICU_INV_COMMRX		(1 << 3)
70
71#endif /* __ASM_MACH_ICU_H */
72