1/*
2 *  Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/memory.h>
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21#include <linux/mtd/nand.h>
22#include <linux/gpio.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28#include <asm/page.h>
29#include <asm/setup.h>
30
31#include "common.h"
32#include "devices-imx31.h"
33#include "hardware.h"
34#include "iomux-mx3.h"
35
36/* FPGA defines */
37#define QONG_FPGA_VERSION(major, minor, rev)	\
38	(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
39
40#define QONG_FPGA_BASEADDR		MX31_CS1_BASE_ADDR
41#define QONG_FPGA_PERIPH_SIZE		(1 << 24)
42
43#define QONG_FPGA_CTRL_BASEADDR		QONG_FPGA_BASEADDR
44#define QONG_FPGA_CTRL_SIZE		0x10
45/* FPGA control registers */
46#define QONG_FPGA_CTRL_VERSION		0x00
47
48#define QONG_DNET_ID		1
49#define QONG_DNET_BASEADDR	\
50	(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
51#define QONG_DNET_SIZE		0x00001000
52
53static const struct imxuart_platform_data uart_pdata __initconst = {
54	.flags = IMXUART_HAVE_RTSCTS,
55};
56
57static int uart_pins[] = {
58	MX31_PIN_CTS1__CTS1,
59	MX31_PIN_RTS1__RTS1,
60	MX31_PIN_TXD1__TXD1,
61	MX31_PIN_RXD1__RXD1
62};
63
64static inline void __init mxc_init_imx_uart(void)
65{
66	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
67			"uart-0");
68	imx31_add_imx_uart0(&uart_pdata);
69}
70
71static struct resource dnet_resources[] = {
72	{
73		.name	= "dnet-memory",
74		.start	= QONG_DNET_BASEADDR,
75		.end	= QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
76		.flags	= IORESOURCE_MEM,
77	}, {
78		/* irq number is run-time assigned */
79		.flags	= IORESOURCE_IRQ,
80	},
81};
82
83static struct platform_device dnet_device = {
84	.name			= "dnet",
85	.id			= -1,
86	.num_resources		= ARRAY_SIZE(dnet_resources),
87	.resource		= dnet_resources,
88};
89
90static int __init qong_init_dnet(void)
91{
92	int ret;
93
94	dnet_resources[1].start =
95		gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
96	dnet_resources[1].end =
97		gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
98	ret = platform_device_register(&dnet_device);
99	return ret;
100}
101
102/* MTD NOR flash */
103
104static struct physmap_flash_data qong_flash_data = {
105	.width = 2,
106};
107
108static struct resource qong_flash_resource = {
109	.start = MX31_CS0_BASE_ADDR,
110	.end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
111	.flags = IORESOURCE_MEM,
112};
113
114static struct platform_device qong_nor_mtd_device = {
115	.name = "physmap-flash",
116	.id = 0,
117	.dev = {
118		.platform_data = &qong_flash_data,
119		},
120	.resource = &qong_flash_resource,
121	.num_resources = 1,
122};
123
124static void qong_init_nor_mtd(void)
125{
126	(void)platform_device_register(&qong_nor_mtd_device);
127}
128
129/*
130 * Hardware specific access to control-lines
131 */
132static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
133{
134	struct nand_chip *nand_chip = mtd->priv;
135
136	if (cmd == NAND_CMD_NONE)
137		return;
138
139	if (ctrl & NAND_CLE)
140		writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
141	else
142		writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
143}
144
145/*
146 * Read the Device Ready pin.
147 */
148static int qong_nand_device_ready(struct mtd_info *mtd)
149{
150	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
151}
152
153static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
154{
155	if (chip >= 0)
156		gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
157	else
158		gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
159}
160
161static struct platform_nand_data qong_nand_data = {
162	.chip = {
163		.nr_chips		= 1,
164		.chip_delay		= 20,
165		.options		= 0,
166	},
167	.ctrl = {
168		.cmd_ctrl		= qong_nand_cmd_ctrl,
169		.dev_ready		= qong_nand_device_ready,
170		.select_chip		= qong_nand_select_chip,
171	}
172};
173
174static struct resource qong_nand_resource = {
175	.start		= MX31_CS3_BASE_ADDR,
176	.end		= MX31_CS3_BASE_ADDR + SZ_32M - 1,
177	.flags		= IORESOURCE_MEM,
178};
179
180static struct platform_device qong_nand_device = {
181	.name		= "gen_nand",
182	.id		= -1,
183	.dev		= {
184		.platform_data = &qong_nand_data,
185	},
186	.num_resources	= 1,
187	.resource	= &qong_nand_resource,
188};
189
190static void __init qong_init_nand_mtd(void)
191{
192	/* init CS */
193	__raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
194	__raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
195	__raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
196
197	mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
198
199	/* enable pin */
200	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
201	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
202		gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
203
204	/* ready/busy pin */
205	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
206	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
207		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
208
209	/* write protect pin */
210	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
211	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
212		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
213
214	platform_device_register(&qong_nand_device);
215}
216
217static void __init qong_init_fpga(void)
218{
219	void __iomem *regs;
220	u32 fpga_ver;
221
222	regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
223	if (!regs) {
224		printk(KERN_ERR "%s: failed to map registers, aborting.\n",
225				__func__);
226		return;
227	}
228
229	fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
230	iounmap(regs);
231	printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
232			(fpga_ver & 0xF000) >> 12,
233			(fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
234	if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
235		printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
236				"devices won't be registered!\n");
237		return;
238	}
239
240	/* register FPGA-based devices */
241	qong_init_nand_mtd();
242	qong_init_dnet();
243}
244
245/*
246 * Board specific initialization.
247 */
248static void __init qong_init(void)
249{
250	imx31_soc_init();
251
252	mxc_init_imx_uart();
253	qong_init_nor_mtd();
254	qong_init_fpga();
255	imx31_add_imx2_wdt();
256}
257
258static void __init qong_timer_init(void)
259{
260	mx31_clocks_init(26000000);
261}
262
263MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
264	/* Maintainer: DENX Software Engineering GmbH */
265	.atag_offset = 0x100,
266	.map_io = mx31_map_io,
267	.init_early = imx31_init_early,
268	.init_irq = mx31_init_irq,
269	.init_time	= qong_timer_init,
270	.init_machine = qong_init,
271	.restart	= mxc_restart,
272MACHINE_END
273