1/*
2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10#include <linux/smp.h>
11#include <linux/io.h>
12#include <linux/of_address.h>
13#include <linux/delay.h>
14
15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h>
17#include <asm/smp_scu.h>
18#include <asm/mach/map.h>
19
20#include "core.h"
21
22#define HIX5HD2_BOOT_ADDRESS		0xffff0000
23
24static void __iomem *ctrl_base;
25
26void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
27{
28	cpu = cpu_logical_map(cpu);
29	if (!cpu || !ctrl_base)
30		return;
31	writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
32}
33
34int hi3xxx_get_cpu_jump(int cpu)
35{
36	cpu = cpu_logical_map(cpu);
37	if (!cpu || !ctrl_base)
38		return 0;
39	return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
40}
41
42static void __init hisi_enable_scu_a9(void)
43{
44	unsigned long base = 0;
45	void __iomem *scu_base = NULL;
46
47	if (scu_a9_has_base()) {
48		base = scu_a9_get_base();
49		scu_base = ioremap(base, SZ_4K);
50		if (!scu_base) {
51			pr_err("ioremap(scu_base) failed\n");
52			return;
53		}
54		scu_enable(scu_base);
55		iounmap(scu_base);
56	}
57}
58
59static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
60{
61	struct device_node *np = NULL;
62	u32 offset = 0;
63
64	hisi_enable_scu_a9();
65	if (!ctrl_base) {
66		np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
67		if (!np) {
68			pr_err("failed to find hisilicon,sysctrl node\n");
69			return;
70		}
71		ctrl_base = of_iomap(np, 0);
72		if (!ctrl_base) {
73			pr_err("failed to map address\n");
74			return;
75		}
76		if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
77			pr_err("failed to find smp-offset property\n");
78			return;
79		}
80		ctrl_base += offset;
81	}
82}
83
84static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
85{
86	hi3xxx_set_cpu(cpu, true);
87	hi3xxx_set_cpu_jump(cpu, secondary_startup);
88	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
89	return 0;
90}
91
92struct smp_operations hi3xxx_smp_ops __initdata = {
93	.smp_prepare_cpus	= hi3xxx_smp_prepare_cpus,
94	.smp_boot_secondary	= hi3xxx_boot_secondary,
95#ifdef CONFIG_HOTPLUG_CPU
96	.cpu_die		= hi3xxx_cpu_die,
97	.cpu_kill		= hi3xxx_cpu_kill,
98#endif
99};
100
101static void __init hisi_common_smp_prepare_cpus(unsigned int max_cpus)
102{
103	hisi_enable_scu_a9();
104}
105
106void hix5hd2_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
107{
108	void __iomem *virt;
109
110	virt = ioremap(start_addr, PAGE_SIZE);
111
112	writel_relaxed(0xe51ff004, virt);	/* ldr pc, [rc, #-4] */
113	writel_relaxed(jump_addr, virt + 4);	/* pc jump phy address */
114	iounmap(virt);
115}
116
117static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
118{
119	phys_addr_t jumpaddr;
120
121	jumpaddr = virt_to_phys(secondary_startup);
122	hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
123	hix5hd2_set_cpu(cpu, true);
124	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
125	return 0;
126}
127
128
129struct smp_operations hix5hd2_smp_ops __initdata = {
130	.smp_prepare_cpus	= hisi_common_smp_prepare_cpus,
131	.smp_boot_secondary	= hix5hd2_boot_secondary,
132#ifdef CONFIG_HOTPLUG_CPU
133	.cpu_die		= hix5hd2_cpu_die,
134#endif
135};
136
137
138#define SC_SCTL_REMAP_CLR      0x00000100
139#define HIP01_BOOT_ADDRESS     0x80000000
140#define REG_SC_CTRL            0x000
141
142void hip01_set_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr)
143{
144	void __iomem *virt;
145
146	virt = phys_to_virt(start_addr);
147
148	writel_relaxed(0xe51ff004, virt);
149	writel_relaxed(jump_addr, virt + 4);
150}
151
152static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
153{
154	phys_addr_t jumpaddr;
155	unsigned int remap_reg_value = 0;
156	struct device_node *node;
157
158
159	jumpaddr = virt_to_phys(secondary_startup);
160	hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
161
162	node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
163	if (WARN_ON(!node))
164		return -1;
165	ctrl_base = of_iomap(node, 0);
166
167	/* set the secondary core boot from DDR */
168	remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
169	barrier();
170	remap_reg_value |= SC_SCTL_REMAP_CLR;
171	barrier();
172	writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
173
174	hip01_set_cpu(cpu, true);
175
176	return 0;
177}
178
179struct smp_operations hip01_smp_ops __initdata = {
180	.smp_prepare_cpus       = hisi_common_smp_prepare_cpus,
181	.smp_boot_secondary     = hip01_boot_secondary,
182};
183
184CPU_METHOD_OF_DECLARE(hi3xxx_smp, "hisilicon,hi3620-smp", &hi3xxx_smp_ops);
185CPU_METHOD_OF_DECLARE(hix5hd2_smp, "hisilicon,hix5hd2-smp", &hix5hd2_smp_ops);
186CPU_METHOD_OF_DECLARE(hip01_smp, "hisilicon,hip01-smp", &hip01_smp_ops);
187