1 /*
2 * linux/arch/arm/mach-clps711x/autcpu12.c
3 *
4 * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/types.h>
23 #include <linux/string.h>
24 #include <linux/mm.h>
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/ioport.h>
28 #include <linux/interrupt.h>
29 #include <linux/mtd/physmap.h>
30 #include <linux/mtd/plat-ram.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/mtd/nand-gpio.h>
33 #include <linux/platform_device.h>
34 #include <linux/basic_mmio_gpio.h>
35
36 #include <mach/hardware.h>
37 #include <asm/sizes.h>
38 #include <asm/setup.h>
39 #include <asm/mach-types.h>
40 #include <asm/mach/arch.h>
41 #include <asm/pgtable.h>
42 #include <asm/page.h>
43
44 #include <asm/mach/map.h>
45
46 #include "common.h"
47 #include "devices.h"
48
49 /* NOR flash */
50 #define AUTCPU12_FLASH_BASE (CS0_PHYS_BASE)
51
52 /* Board specific hardware definitions */
53 #define AUTCPU12_CHAR_LCD_BASE (CS1_PHYS_BASE + 0x00000000)
54 #define AUTCPU12_CSAUX1_BASE (CS1_PHYS_BASE + 0x04000000)
55 #define AUTCPU12_CAN_BASE (CS1_PHYS_BASE + 0x08000000)
56 #define AUTCPU12_TOUCH_BASE (CS1_PHYS_BASE + 0x0a000000)
57 #define AUTCPU12_IO_BASE (CS1_PHYS_BASE + 0x0c000000)
58 #define AUTCPU12_LPT_BASE (CS1_PHYS_BASE + 0x0e000000)
59
60 /* NVRAM */
61 #define AUTCPU12_NVRAM_BASE (CS1_PHYS_BASE + 0x02000000)
62
63 /* SmartMedia flash */
64 #define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
65 #define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
66
67 /* Ethernet */
68 #define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
69 #define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
70
71 /* NAND flash */
72 #define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
73 #define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
74 #define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
75 #define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
76 #define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 4)
77
78 /* LCD contrast digital potentiometer */
79 #define AUTCPU12_DPOT_CS CLPS711X_GPIO(4, 0)
80 #define AUTCPU12_DPOT_CLK CLPS711X_GPIO(4, 1)
81 #define AUTCPU12_DPOT_UD CLPS711X_GPIO(4, 2)
82
83 static struct resource autcpu12_cs8900_resource[] __initdata = {
84 DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
85 DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
86 };
87
88 static struct resource autcpu12_nand_resource[] __initdata = {
89 DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
90 };
91
92 static struct mtd_partition autcpu12_nand_parts[] __initdata = {
93 {
94 .name = "Flash partition 1",
95 .offset = 0,
96 .size = SZ_8M,
97 },
98 {
99 .name = "Flash partition 2",
100 .offset = MTDPART_OFS_APPEND,
101 .size = MTDPART_SIZ_FULL,
102 },
103 };
104
autcpu12_adjust_parts(struct gpio_nand_platdata * pdata,size_t sz)105 static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
106 size_t sz)
107 {
108 switch (sz) {
109 case SZ_16M:
110 case SZ_32M:
111 break;
112 case SZ_64M:
113 case SZ_128M:
114 pdata->parts[0].size = SZ_16M;
115 break;
116 default:
117 pr_warn("Unsupported SmartMedia device size %u\n", sz);
118 break;
119 }
120 }
121
122 static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
123 .gpio_rdy = AUTCPU12_SMC_RDY,
124 .gpio_nce = AUTCPU12_SMC_NCE,
125 .gpio_ale = AUTCPU12_SMC_ALE,
126 .gpio_cle = AUTCPU12_SMC_CLE,
127 .gpio_nwp = -1,
128 .chip_delay = 20,
129 .parts = autcpu12_nand_parts,
130 .num_parts = ARRAY_SIZE(autcpu12_nand_parts),
131 .adjust_parts = autcpu12_adjust_parts,
132 };
133
134 static struct platform_device autcpu12_nand_pdev __initdata = {
135 .name = "gpio-nand",
136 .id = -1,
137 .resource = autcpu12_nand_resource,
138 .num_resources = ARRAY_SIZE(autcpu12_nand_resource),
139 .dev = {
140 .platform_data = &autcpu12_nand_pdata,
141 },
142 };
143
144 static struct resource autcpu12_mmgpio_resource[] __initdata = {
145 DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
146 };
147
148 static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
149 .base = AUTCPU12_MMGPIO_BASE,
150 .ngpio = 8,
151 };
152
153 static struct platform_device autcpu12_mmgpio_pdev __initdata = {
154 .name = "basic-mmio-gpio",
155 .id = -1,
156 .resource = autcpu12_mmgpio_resource,
157 .num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
158 .dev = {
159 .platform_data = &autcpu12_mmgpio_pdata,
160 },
161 };
162
163 static const struct gpio const autcpu12_gpios[] __initconst = {
164 { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
165 { AUTCPU12_DPOT_CLK, GPIOF_OUT_INIT_LOW, "DPOT CLK" },
166 { AUTCPU12_DPOT_UD, GPIOF_OUT_INIT_LOW, "DPOT UD" },
167 };
168
169 static struct mtd_partition autcpu12_flash_partitions[] = {
170 {
171 .name = "NOR.0",
172 .offset = 0,
173 .size = MTDPART_SIZ_FULL,
174 },
175 };
176
177 static struct physmap_flash_data autcpu12_flash_pdata = {
178 .width = 4,
179 .parts = autcpu12_flash_partitions,
180 .nr_parts = ARRAY_SIZE(autcpu12_flash_partitions),
181 };
182
183 static struct resource autcpu12_flash_resources[] __initdata = {
184 DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
185 };
186
187 static struct platform_device autcpu12_flash_pdev __initdata = {
188 .name = "physmap-flash",
189 .id = 0,
190 .resource = autcpu12_flash_resources,
191 .num_resources = ARRAY_SIZE(autcpu12_flash_resources),
192 .dev = {
193 .platform_data = &autcpu12_flash_pdata,
194 },
195 };
196
197 static struct resource autcpu12_nvram_resource[] __initdata = {
198 DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
199 };
200
201 static struct platdata_mtd_ram autcpu12_nvram_pdata = {
202 .bankwidth = 4,
203 };
204
205 static struct platform_device autcpu12_nvram_pdev __initdata = {
206 .name = "mtd-ram",
207 .id = 0,
208 .resource = autcpu12_nvram_resource,
209 .num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
210 .dev = {
211 .platform_data = &autcpu12_nvram_pdata,
212 },
213 };
214
autcpu12_nvram_init(void)215 static void __init autcpu12_nvram_init(void)
216 {
217 void __iomem *nvram;
218 unsigned int save[2];
219 resource_size_t nvram_size = SZ_128K;
220
221 /*
222 * Check for 32K/128K
223 * Read ofs 0K
224 * Read ofs 64K
225 * Write complement to ofs 64K
226 * Read and check result on ofs 0K
227 * Restore contents
228 */
229 nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
230 if (nvram) {
231 save[0] = readl(nvram + 0);
232 save[1] = readl(nvram + SZ_64K);
233 writel(~save[0], nvram + SZ_64K);
234 if (readl(nvram + 0) != save[0]) {
235 writel(save[0], nvram + 0);
236 nvram_size = SZ_32K;
237 } else
238 writel(save[1], nvram + SZ_64K);
239 iounmap(nvram);
240
241 autcpu12_nvram_resource[0].end =
242 autcpu12_nvram_resource[0].start + nvram_size - 1;
243 platform_device_register(&autcpu12_nvram_pdev);
244 } else
245 pr_err("Failed to remap NVRAM resource\n");
246 }
247
autcpu12_init(void)248 static void __init autcpu12_init(void)
249 {
250 clps711x_devices_init();
251 platform_device_register(&autcpu12_flash_pdev);
252 platform_device_register_simple("video-clps711x", 0, NULL, 0);
253 platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
254 ARRAY_SIZE(autcpu12_cs8900_resource));
255 platform_device_register(&autcpu12_mmgpio_pdev);
256 autcpu12_nvram_init();
257 }
258
autcpu12_init_late(void)259 static void __init autcpu12_init_late(void)
260 {
261 gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
262 platform_device_register(&autcpu12_nand_pdev);
263 }
264
265 MACHINE_START(AUTCPU12, "autronix autcpu12")
266 /* Maintainer: Thomas Gleixner */
267 .atag_offset = 0x20000,
268 .map_io = clps711x_map_io,
269 .init_irq = clps711x_init_irq,
270 .init_time = clps711x_timer_init,
271 .init_machine = autcpu12_init,
272 .init_late = autcpu12_init_late,
273 .restart = clps711x_restart,
274 MACHINE_END
275
276