1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "ste-dbx5x0.dtsi"
13#include "ste-href-ab8500.dtsi"
14#include "ste-href.dtsi"
15
16/ {
17	model = "ST-Ericsson HREF (v60+) platform with Device Tree";
18	compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
19
20	soc {
21		// External Micro SD slot
22		sdi0_per1@80126000 {
23			cd-gpios  = <&gpio2 31 0x4>; // 95
24		};
25
26		vmmci: regulator-gpio {
27			gpios = <&gpio0 5 0x4>;
28			enable-gpio = <&gpio5 9 0x4>;
29		};
30
31		pinctrl {
32			/*
33			 * Set this up using hogs, as time goes by and as seems fit, these
34			 * can be moved over to being controlled by respective device.
35			 */
36			pinctrl-names = "default";
37			pinctrl-0 = <&ipgpio_hrefv60_mode>,
38				  <&etm_hrefv60_mode>,
39				  <&nahj_hrefv60_mode>,
40				  <&nfc_hrefv60_mode>,
41				  <&force_hrefv60_mode>,
42				  <&dipro_hrefv60_mode>,
43				  <&vaudio_hf_hrefv60_mode>,
44				  <&gbf_hrefv60_mode>,
45				  <&hdtv_hrefv60_mode>,
46				  <&touch_hrefv60_mode>,
47				  <&gpios_hrefv60_mode>;
48
49			sdi0 {
50				sdi0_default_mode: sdi0_default {
51					/* SD card detect GPIO pin, extend default state */
52					default_hrefv60_cfg1 {
53						pins = "GPIO95_E8";
54						ste,config = <&gpio_in_pu>;
55					};
56					/* VMMCI level-shifter enable */
57					default_hrefv60_cfg2 {
58						pins = "GPIO169_D22";
59						ste,config = <&gpio_out_hi>;
60					};
61					/* VMMCI level-shifter voltage select */
62					default_hrefv60_cfg3 {
63						pins = "GPIO5_AG6";
64						ste,config = <&gpio_out_hi>;
65					};
66				};
67			};
68			ipgpio {
69				/*
70				 * XENON Flashgun on image processor GPIO (controlled from image
71				 * processor firmware), mux in these image processor GPIO lines 0
72				 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
73				 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
74				 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
75				 */
76				ipgpio_hrefv60_mode: ipgpio_hrefv60 {
77					hrefv60_mux {
78						function = "ipgpio";
79						groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
80					};
81					hrefv60_cfg1 {
82						pins = "GPIO6_AF6", "GPIO7_AG5";
83						ste,config = <&in_pu>;
84					};
85					hrefv60_cfg2 {
86						pins = "GPIO21_AB3";
87						ste,config = <&gpio_out_lo>;
88					};
89					hrefv60_cfg3 {
90						pins = "GPIO64_F3";
91						ste,config = <&out_lo>;
92					};
93				};
94			};
95			etm {
96				/*
97				 * Drive D19-D23 for the ETM PTM trace interface low,
98				 * (presumably pins are unconnected therefore grounded here,
99				 * the "other alt C1" setting enables these pins)
100				 */
101				etm_hrefv60_mode: etm_hrefv60 {
102					hrefv60_cfg1 {
103						pins =
104						"GPIO70_G5",
105						"GPIO71_G4",
106						"GPIO72_H4",
107						"GPIO73_H3",
108						"GPIO74_J3";
109						ste,config = <&gpio_out_lo>;
110					};
111				 };
112			};
113			nahj {
114				nahj_hrefv60_mode: nahj_hrefv60 {
115					/* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
116					hrefv60_cfg1 {
117						pins = "GPIO76_J2";
118						ste,config = <&gpio_out_lo>;
119					};
120					hrefv60_cfg2 {
121						pins = "GPIO216_AG12";
122						ste,config = <&gpio_out_hi>;
123					};
124				 };
125			};
126			nfc {
127				nfc_hrefv60_mode: nfc_hrefv60 {
128					/* NFC ENA and RESET to low, pulldown IRQ line */
129					hrefv60_cfg1 {
130						pins =
131						"GPIO77_H1", /* NFC_ENA */
132						"GPIO142_C11"; /* NFC_RESET */
133						ste,config = <&gpio_out_lo>;
134					};
135					hrefv60_cfg2 {
136						pins = "GPIO144_B13"; /* NFC_IRQ */
137						ste,config = <&gpio_in_pd>;
138					};
139				 };
140			};
141			force {
142				force_hrefv60_mode: force_hrefv60 {
143					hrefv60_cfg1 {
144						pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
145						ste,config = <&gpio_in_pu>;
146					};
147					hrefv60_cfg2 {
148						pins =
149						"GPIO92_D6", /* FORCE_SENSING_RST */
150						"GPIO97_D9"; /* FORCE_SENSING_WU */
151						ste,config = <&gpio_out_lo>;
152					};
153				 };
154			};
155			dipro {
156				dipro_hrefv60_mode: dipro_hrefv60 {
157					hrefv60_cfg1 {
158						pins = "GPIO139_C9"; /* DIPRO_INT */
159						ste,config = <&gpio_in_pu>;
160					};
161				 };
162			};
163			vaudio_hf {
164				vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
165					/* Audio Amplifier HF enable GPIO */
166					hrefv60_cfg1 {
167						pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
168						ste,config = <&gpio_out_hi>;
169					};
170				 };
171			};
172			gbf {
173				gbf_hrefv60_mode: gbf_hrefv60 {
174					/*
175					 * GBF (GPS, Bluetooth, FM-radio) interface,
176					 * pull low to reset state
177					 */
178					hrefv60_cfg1 {
179						pins = "GPIO171_D23"; /* GBF_ENA_RESET */
180						ste,config = <&gpio_out_lo>;
181					};
182				 };
183			};
184			hdtv {
185				hdtv_hrefv60_mode: hdtv_hrefv60 {
186					/* MSP : HDTV INTERFACE GPIO line */
187					hrefv60_cfg1 {
188						pins = "GPIO192_AJ27";
189						ste,config = <&gpio_in_pd>;
190					};
191				 };
192			};
193			touch {
194				touch_hrefv60_mode: touch_hrefv60 {
195					/*
196					 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
197					 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
198					 * reset signals low.
199					 */
200					hrefv60_cfg1 {
201						pins = "GPIO143_D12", "GPIO146_D13";
202						ste,config = <&gpio_out_lo>;
203					};
204					hrefv60_cfg2 {
205						pins = "GPIO67_G2";
206						ste,config = <&gpio_in_pu>;
207					};
208				};
209			};
210			mcde {
211				lcd_hrefv60_mode: lcd_hrefv60 {
212					/*
213					 * Display Interface 1 uses GPIO 65 for RST (reset).
214					 * Display Interface 2 uses GPIO 66 for RST (reset).
215					 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
216					 */
217					hrefv60_cfg1 {
218						pins ="GPIO65_F1";
219						ste,config = <&gpio_out_hi>;
220					};
221					hrefv60_cfg2 {
222						pins ="GPIO66_G3";
223						ste,config = <&gpio_out_lo>;
224					};
225				};
226			};
227			gpios {
228				/* Dangling GPIO pins */
229				gpios_hrefv60_mode: gpios_hrefv60 {
230					default_cfg1 {
231						/* Normally UART1 RXD, now dangling */
232						pins = "GPIO4_AH6";
233						ste,config = <&in_pu>;
234					};
235				};
236			};
237		};
238	};
239};
240