1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/input/input.h>
12#include "imx6ul.dtsi"
13
14/ {
15	model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
16	compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
17
18	chosen {
19		stdout-path = &uart1;
20	};
21
22	memory {
23		reg = <0x80000000 0x20000000>;
24	};
25
26	regulators {
27		compatible = "simple-bus";
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		reg_sd1_vmmc: sd1_regulator {
32			compatible = "regulator-fixed";
33			regulator-name = "VSD_3V3";
34			regulator-min-microvolt = <3300000>;
35			regulator-max-microvolt = <3300000>;
36			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
37			enable-active-high;
38		};
39	};
40};
41
42&cpu0 {
43	arm-supply = <&reg_arm>;
44	soc-supply = <&reg_soc>;
45};
46
47&fec1 {
48	pinctrl-names = "default";
49	pinctrl-0 = <&pinctrl_enet1>;
50	phy-mode = "rmii";
51	phy-handle = <&ethphy0>;
52	status = "okay";
53};
54
55&fec2 {
56	pinctrl-names = "default";
57	pinctrl-0 = <&pinctrl_enet2>;
58	phy-mode = "rmii";
59	phy-handle = <&ethphy1>;
60	status = "okay";
61
62	mdio {
63		#address-cells = <1>;
64		#size-cells = <0>;
65
66		ethphy0: ethernet-phy@2 {
67			reg = <2>;
68		};
69
70		ethphy1: ethernet-phy@1 {
71			reg = <1>;
72		};
73	};
74};
75
76&qspi {
77	pinctrl-names = "default";
78	pinctrl-0 = <&pinctrl_qspi>;
79	status = "okay";
80
81	flash0: n25q256a@0 {
82		#address-cells = <1>;
83		#size-cells = <1>;
84		compatible = "micron,n25q256a";
85		spi-max-frequency = <29000000>;
86		reg = <0>;
87	};
88};
89
90&snvs_poweroff {
91	status = "okay";
92};
93
94&tsc {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_tsc>;
97	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
98	measure-delay-time = <0xffff>;
99	pre-charge-time = <0xfff>;
100	status = "okay";
101};
102
103&uart1 {
104	pinctrl-names = "default";
105	pinctrl-0 = <&pinctrl_uart1>;
106	status = "okay";
107};
108
109&uart2 {
110	pinctrl-names = "default";
111	pinctrl-0 = <&pinctrl_uart2>;
112	fsl,uart-has-rtscts;
113	status = "okay";
114};
115
116&usbotg1 {
117	dr_mode = "peripheral";
118	status = "okay";
119};
120
121&usbotg2 {
122	dr_mode = "host";
123	disable-over-current;
124	status = "okay";
125};
126
127&usdhc1 {
128	pinctrl-names = "default", "state_100mhz", "state_200mhz";
129	pinctrl-0 = <&pinctrl_usdhc1>;
130	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
131	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
132	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
133	keep-power-in-suspend;
134	enable-sdio-wakeup;
135	vmmc-supply = <&reg_sd1_vmmc>;
136	status = "okay";
137};
138
139&usdhc2 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_usdhc2>;
142	no-1-8-v;
143	keep-power-in-suspend;
144	enable-sdio-wakeup;
145	status = "okay";
146};
147
148&iomuxc {
149	pinctrl-names = "default";
150
151	pinctrl_csi1: csi1grp {
152		fsl,pins = <
153			MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
154			MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
155			MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
156			MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
157			MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
158			MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
159			MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
160			MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
161			MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
162			MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
163			MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
164			MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
165		>;
166	};
167
168	pinctrl_enet1: enet1grp {
169		fsl,pins = <
170			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
171			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
172			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
173			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
174			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
175			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
176			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
177			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
178		>;
179	};
180
181	pinctrl_enet2: enet2grp {
182		fsl,pins = <
183			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
184			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
185			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
186			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
187			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
188			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
189			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
190			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
191			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
192			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
193			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x17059
194		>;
195	};
196
197	pinctrl_flexcan1: flexcan1grp{
198		fsl,pins = <
199			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
200			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
201		>;
202	};
203
204	pinctrl_flexcan2: flexcan2grp{
205		fsl,pins = <
206			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
207			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
208		>;
209	};
210
211	pinctrl_i2c1: i2c1grp {
212		fsl,pins = <
213			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
214			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
215		>;
216	};
217
218	pinctrl_i2c2: i2c2grp {
219		fsl,pins = <
220			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
221			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
222		>;
223	};
224
225	pinctrl_lcdif_dat: lcdifdatgrp {
226		fsl,pins = <
227			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
228			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
229			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
230			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
231			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
232			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
233			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
234			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
235			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
236			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
237			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
238			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
239			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
240			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
241			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
242			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
243			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
244			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
245			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
246			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
247			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
248			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
249			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
250			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
251		>;
252	};
253
254	pinctrl_lcdif_ctrl: lcdifctrlgrp {
255		fsl,pins = <
256			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
257			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
258			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
259			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
260			/* used for lcd reset */
261			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
262		>;
263	};
264
265	pinctrl_qspi: qspigrp {
266		fsl,pins = <
267			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK	0x70a1
268			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00	0x70a1
269			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01	0x70a1
270			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02	0x70a1
271			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03	0x70a1
272			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B	0x70a1
273		>;
274	};
275
276	pinctrl_pwm1: pwm1grp {
277		fsl,pins = <
278			MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
279		>;
280	};
281
282	pinctrl_sim2: sim2grp {
283		fsl,pins = <
284			MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0xb808
285			MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x31
286			MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0xb808
287			MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0xb808
288			MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0xb809
289			MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x3008
290		>;
291	};
292
293	pinctrl_tsc: tscgrp {
294		fsl,pins = <
295			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01		0xb0
296			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02		0xb0
297			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03		0xb0
298			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04		0xb0
299		>;
300	};
301
302	pinctrl_uart1: uart1grp {
303		fsl,pins = <
304			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
305			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
306		>;
307	};
308
309	pinctrl_uart2: uart2grp {
310		fsl,pins = <
311			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
312			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
313			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
314			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
315		>;
316	};
317
318	pinctrl_usdhc1: usdhc1grp {
319		fsl,pins = <
320			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
321			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
322			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
323			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
324			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
325			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
326			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
327			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
328			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
329		>;
330	};
331
332	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
333		fsl,pins = <
334			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
335			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
336			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
337			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
338			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
339			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
340
341		>;
342	};
343
344	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
345		fsl,pins = <
346			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
347			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
348			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
349			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
350			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
351			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
352		>;
353	};
354
355	pinctrl_usdhc2: usdhc2grp {
356		fsl,pins = <
357			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
358			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
359			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
360			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
361			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
362			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
363		>;
364	};
365};
366