1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx1.dtsi"
14
15/ {
16	model = "Freescale MX1 ADS";
17	compatible = "fsl,imx1ads", "fsl,imx1";
18
19	chosen {
20		stdout-path = &uart1;
21	};
22
23	memory {
24		reg = <0x08000000 0x04000000>;
25	};
26
27	clocks {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		clk32 {
32			compatible = "fsl,imx-clk32", "fixed-clock";
33			#clock-cells = <0>;
34			clock-frequency = <32000>;
35		};
36	};
37};
38
39&cspi1 {
40	pinctrl-0 = <&pinctrl_cspi1>;
41	fsl,spi-num-chipselects = <1>;
42	cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
43	status = "okay";
44};
45
46&i2c {
47	pinctrl-names = "default";
48	pinctrl-0 = <&pinctrl_i2c>;
49	status = "okay";
50
51	extgpio0: pcf8575@22 {
52		compatible = "nxp,pcf8575";
53		reg = <0x22>;
54		gpio-controller;
55		#gpio-cells = <2>;
56	};
57
58	extgpio1: pcf8575@24 {
59		compatible = "nxp,pcf8575";
60		reg = <0x24>;
61		gpio-controller;
62		#gpio-cells = <2>;
63	};
64};
65
66&uart1 {
67	pinctrl-names = "default";
68	pinctrl-0 = <&pinctrl_uart1>;
69	fsl,uart-has-rtscts;
70	status = "okay";
71};
72
73&uart2 {
74	pinctrl-names = "default";
75	pinctrl-0 = <&pinctrl_uart2>;
76	fsl,uart-has-rtscts;
77	status = "okay";
78};
79
80&weim {
81	pinctrl-names = "default";
82	pinctrl-0 = <&pinctrl_weim>;
83	status = "okay";
84
85	nor: nor@0,0 {
86		compatible = "cfi-flash";
87		reg = <0 0x00000000 0x02000000>;
88		bank-width = <4>;
89		fsl,weim-cs-timing = <0x00003e00 0x00000801>;
90		#address-cells = <1>;
91		#size-cells = <1>;
92	};
93};
94
95&iomuxc {
96	imx1-ads {
97		pinctrl_cspi1: cspi1grp {
98			fsl,pins = <
99				MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
100				MX1_PAD_SPI1_MOSI__SPI1_MOSI	0x0
101				MX1_PAD_SPI1_RDY__SPI1_RDY	0x0
102				MX1_PAD_SPI1_SCLK__SPI1_SCLK	0x0
103				MX1_PAD_SPI1_SS__GPIO3_15	0x0
104			>;
105		};
106
107		pinctrl_i2c: i2cgrp {
108			fsl,pins = <
109				MX1_PAD_I2C_SCL__I2C_SCL	0x0
110				MX1_PAD_I2C_SDA__I2C_SDA	0x0
111			>;
112		};
113
114		pinctrl_uart1: uart1grp {
115			fsl,pins = <
116				MX1_PAD_UART1_TXD__UART1_TXD	0x0
117				MX1_PAD_UART1_RXD__UART1_RXD	0x0
118				MX1_PAD_UART1_CTS__UART1_CTS	0x0
119				MX1_PAD_UART1_RTS__UART1_RTS	0x0
120			>;
121		};
122
123		pinctrl_uart2: uart2grp {
124			fsl,pins = <
125				MX1_PAD_UART2_TXD__UART2_TXD	0x0
126				MX1_PAD_UART2_RXD__UART2_RXD	0x0
127				MX1_PAD_UART2_CTS__UART2_CTS	0x0
128				MX1_PAD_UART2_RTS__UART2_RTS	0x0
129			>;
130		};
131
132		pinctrl_weim: weimgrp {
133			fsl,pins = <
134				MX1_PAD_A0__A0			0x0
135				MX1_PAD_A16__A16		0x0
136				MX1_PAD_A17__A17		0x0
137				MX1_PAD_A18__A18		0x0
138				MX1_PAD_A19__A19		0x0
139				MX1_PAD_A20__A20		0x0
140				MX1_PAD_A21__A21		0x0
141				MX1_PAD_A22__A22		0x0
142				MX1_PAD_A23__A23		0x0
143				MX1_PAD_A24__A24		0x0
144				MX1_PAD_BCLK__BCLK		0x0
145				MX1_PAD_CS4__CS4		0x0
146				MX1_PAD_DTACK__DTACK		0x0
147				MX1_PAD_ECB__ECB		0x0
148				MX1_PAD_LBA__LBA		0x0
149			>;
150		};
151	};
152};
153