1/*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_ARC_MMU_H
10#define _ASM_ARC_MMU_H
11
12#if defined(CONFIG_ARC_MMU_V1)
13#define CONFIG_ARC_MMU_VER 1
14#elif defined(CONFIG_ARC_MMU_V2)
15#define CONFIG_ARC_MMU_VER 2
16#elif defined(CONFIG_ARC_MMU_V3)
17#define CONFIG_ARC_MMU_VER 3
18#elif defined(CONFIG_ARC_MMU_V4)
19#define CONFIG_ARC_MMU_VER 4
20#endif
21
22/* MMU Management regs */
23#define ARC_REG_MMU_BCR		0x06f
24#if (CONFIG_ARC_MMU_VER < 4)
25#define ARC_REG_TLBPD0		0x405
26#define ARC_REG_TLBPD1		0x406
27#define ARC_REG_TLBPD1HI	0	/* Dummy: allows code sharing with ARC700 */
28#define ARC_REG_TLBINDEX	0x407
29#define ARC_REG_TLBCOMMAND	0x408
30#define ARC_REG_PID		0x409
31#define ARC_REG_SCRATCH_DATA0	0x418
32#else
33#define ARC_REG_TLBPD0		0x460
34#define ARC_REG_TLBPD1		0x461
35#define ARC_REG_TLBPD1HI	0x463
36#define ARC_REG_TLBINDEX	0x464
37#define ARC_REG_TLBCOMMAND	0x465
38#define ARC_REG_PID		0x468
39#define ARC_REG_SCRATCH_DATA0	0x46c
40#endif
41
42/* Bits in MMU PID register */
43#define __TLB_ENABLE		(1 << 31)
44#define __PROG_ENABLE		(1 << 30)
45#define MMU_ENABLE		(__TLB_ENABLE | __PROG_ENABLE)
46
47/* Error code if probe fails */
48#define TLB_LKUP_ERR		0x80000000
49
50#if (CONFIG_ARC_MMU_VER < 4)
51#define TLB_DUP_ERR	(TLB_LKUP_ERR | 0x00000001)
52#else
53#define TLB_DUP_ERR	(TLB_LKUP_ERR | 0x40000000)
54#endif
55
56/* TLB Commands */
57#define TLBWrite    0x1
58#define TLBRead     0x2
59#define TLBGetIndex 0x3
60#define TLBProbe    0x4
61
62#if (CONFIG_ARC_MMU_VER >= 2)
63#define TLBWriteNI  0x5		/* write JTLB without inv uTLBs */
64#define TLBIVUTLB   0x6		/* explicitly inv uTLBs */
65#endif
66
67#if (CONFIG_ARC_MMU_VER >= 4)
68#define TLBInsertEntry	0x7
69#define TLBDeleteEntry	0x8
70#endif
71
72#ifndef __ASSEMBLY__
73
74typedef struct {
75	unsigned long asid[NR_CPUS];	/* 8 bit MMU PID + Generation cycle */
76} mm_context_t;
77
78#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
79void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
80#else
81#define tlb_paranoid_check(a, b)
82#endif
83
84void arc_mmu_init(void);
85extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
86void read_decode_mmu_bcr(void);
87
88static inline int is_pae40_enabled(void)
89{
90	return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
91}
92
93#endif	/* !__ASSEMBLY__ */
94
95#endif
96