1 DSCR (Data Stream Control Register) 2 ================================================ 3 4DSCR register in powerpc allows user to have some control of prefetch of data 5stream in the processor. Please refer to the ISA documents or related manual 6for more detailed information regarding how to use this DSCR to attain this 7control of the prefetches . This document here provides an overview of kernel 8support for DSCR, related kernel objects, it's functionalities and exported 9user interface. 10 11(A) Data Structures: 12 13 (1) thread_struct: 14 dscr /* Thread DSCR value */ 15 dscr_inherit /* Thread has changed default DSCR */ 16 17 (2) PACA: 18 dscr_default /* per-CPU DSCR default value */ 19 20 (3) sysfs.c: 21 dscr_default /* System DSCR default value */ 22 23(B) Scheduler Changes: 24 25 Scheduler will write the per-CPU DSCR default which is stored in the 26 CPU's PACA value into the register if the thread has dscr_inherit value 27 cleared which means that it has not changed the default DSCR till now. 28 If the dscr_inherit value is set which means that it has changed the 29 default DSCR value, scheduler will write the changed value which will 30 now be contained in thread struct's dscr into the register instead of 31 the per-CPU default PACA based DSCR value. 32 33 NOTE: Please note here that the system wide global DSCR value never 34 gets used directly in the scheduler process context switch at all. 35 36(C) SYSFS Interface: 37 38 Global DSCR default: /sys/devices/system/cpu/dscr_default 39 CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr 40 41 Changing the global DSCR default in the sysfs will change all the CPU 42 specific DSCR defaults immediately in their PACA structures. Again if 43 the current process has the dscr_inherit clear, it also writes the new 44 value into every CPU's DSCR register right away and updates the current 45 thread's DSCR value as well. 46 47 Changing the CPU specific DSCR default value in the sysfs does exactly 48 the same thing as above but unlike the global one above, it just changes 49 stuff for that particular CPU instead for all the CPUs on the system. 50 51(D) User Space Instructions: 52 53 The DSCR register can be accessed in the user space using any of these 54 two SPR numbers available for that purpose. 55 56 (1) Problem state SPR: 0x03 (Un-privileged, POWER8 only) 57 (2) Privileged state SPR: 0x11 (Privileged) 58 59 Accessing DSCR through privileged SPR number (0x11) from user space 60 works, as it is emulated following an illegal instruction exception 61 inside the kernel. Both mfspr and mtspr instructions are emulated. 62 63 Accessing DSCR through user level SPR (0x03) from user space will first 64 create a facility unavailable exception. Inside this exception handler 65 all mfspr instruction based read attempts will get emulated and returned 66 where as the first mtspr instruction based write attempts will enable 67 the DSCR facility for the next time around (both for read and write) by 68 setting DSCR facility in the FSCR register. 69 70(E) Specifics about 'dscr_inherit': 71 72 The thread struct element 'dscr_inherit' represents whether the thread 73 in question has attempted and changed the DSCR itself using any of the 74 following methods. This element signifies whether the thread wants to 75 use the CPU default DSCR value or its own changed DSCR value in the 76 kernel. 77 78 (1) mtspr instruction (SPR number 0x03) 79 (2) mtspr instruction (SPR number 0x11) 80 (3) ptrace interface (Explicitly set user DSCR value) 81 82 Any child of the process created after this event in the process inherits 83 this same behaviour as well. 84