1Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
2-------------------------------------------------------------------
3
4Required properties:
5- compatible		: Should be "xlnx,zynqmp-qspi-1.0".
6- reg			: Physical base address and size of GQSPI registers map.
7- interrupts		: Property with a value describing the interrupt
8			  number.
9- interrupt-parent	: Must be core interrupt controller.
10- clock-names		: List of input clock names - "ref_clk", "pclk"
11			  (See clock bindings for details).
12- clocks		: Clock phandles (see clock bindings for details).
13
14Optional properties:
15- num-cs		: Number of chip selects used.
16
17Example:
18	qspi: spi@ff0f0000 {
19		compatible = "xlnx,zynqmp-qspi-1.0";
20		clock-names = "ref_clk", "pclk";
21		clocks = <&misc_clk &misc_clk>;
22		interrupts = <0 15 4>;
23		interrupt-parent = <&gic>;
24		num-cs = <1>;
25		reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
26	};
27