1Qualcomm DWC3 HS AND SS PHY CONTROLLER
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3
4DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
5controllers.  Each DWC3 PHY controller should have its own node.
6
7Required properties:
8- compatible: should contain one of the following:
9	- "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
10	- "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
11- reg: offset and length of the DWC3 PHY controller register set
12- #phy-cells: must be zero
13- clocks: a list of phandles and clock-specifier pairs, one for each entry in
14  clock-names.
15- clock-names: Should contain "ref" for the PHY reference clock
16
17Optional clocks:
18  "xo"		External reference clock
19
20Example:
21		phy@100f8800 {
22			compatible = "qcom,dwc3-hs-usb-phy";
23			reg = <0x100f8800 0x30>;
24			clocks = <&gcc USB30_0_UTMI_CLK>;
25			clock-names = "ref";
26			#phy-cells = <0>;
27
28			status = "ok";
29		};
30
31		phy@100f8830 {
32			compatible = "qcom,dwc3-ss-usb-phy";
33			reg = <0x100f8830 0x30>;
34			clocks = <&gcc USB30_0_MASTER_CLK>;
35			clock-names = "ref";
36			#phy-cells = <0>;
37
38			status = "ok";
39		};
40