1mt65xx USB3.0 PHY binding
2--------------------------
3
4This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
5
6Required properties (controller (parent) node):
7 - compatible	: should be "mediatek,mt8173-u3phy"
8 - reg		: offset and length of register for phy, exclude port's
9		  register.
10 - clocks	: a list of phandle + clock-specifier pairs, one for each
11		  entry in clock-names
12 - clock-names	: must contain
13		  "u3phya_ref": for reference clock of usb3.0 analog phy.
14
15Required nodes	: a sub-node is required for each port the controller
16		  provides. Address range information including the usual
17		  'reg' property is used inside these nodes to describe
18		  the controller's topology.
19
20Required properties (port (child) node):
21- reg		: address and length of the register set for the port.
22- #phy-cells	: should be 1 (See second example)
23		  cell after port phandle is phy type from:
24			- PHY_TYPE_USB2
25			- PHY_TYPE_USB3
26
27Example:
28
29u3phy: usb-phy@11290000 {
30	compatible = "mediatek,mt8173-u3phy";
31	reg = <0 0x11290000 0 0x800>;
32	clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
33	clock-names = "u3phya_ref";
34	#address-cells = <2>;
35	#size-cells = <2>;
36	ranges;
37	status = "okay";
38
39	phy_port0: port@11290800 {
40		reg = <0 0x11290800 0 0x800>;
41		#phy-cells = <1>;
42		status = "okay";
43	};
44
45	phy_port1: port@11291000 {
46		reg = <0 0x11291000 0 0x800>;
47		#phy-cells = <1>;
48		status = "okay";
49	};
50};
51
52Specifying phy control of devices
53---------------------------------
54
55Device nodes should specify the configuration required in their "phys"
56property, containing a phandle to the phy port node and a device type;
57phy-names for each port are optional.
58
59Example:
60
61#include <dt-bindings/phy/phy.h>
62
63usb30: usb@11270000 {
64	...
65	phys = <&phy_port0 PHY_TYPE_USB3>;
66	phy-names = "usb3-0";
67	...
68};
69