1ST Microelectronics Flexible Static Memory Controller (FSMC)
2NAND Interface
3
4Required properties:
5- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6- reg : Address range of the mtd chip
7- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
8
9Optional properties:
10- bank-width : Width (in bytes) of the device.  If not present, the width
11  defaults to 1 byte
12- nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13- timings: array of 6 bytes for NAND timings. The meanings of these bytes
14  are:
15  byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
16                 are valid. Zero means one clockcycle, 15 means 16 clock
17                 cycles.
18  byte 1 TAR   : ALE to RE delay, 4 bits are valid. Same format as TCLR.
19  byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
20                 kept in Hi-Z (tristate) after the start of a write access.
21                 Only valid for write transactions. Zero means zero cycles,
22                 255 means 255 cycles.
23  byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
24                 when writing) after the command deassertation. Zero means
25                 one cycle, 255 means 256 cycles.
26  byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
27                 NAND flash in response to SMWAITn. Zero means 1 cycle,
28                 255 means 256 cycles.
29  byte 5 TSET  : number of HCLK clock cycles to assert the address before the
30                 command is asserted. Zero means one cycle, 255 means 256
31                 cycles.
32- bank: default NAND bank to use (0-3 are valid, 0 is the default).
33- nand-ecc-mode      : see nand.txt
34- nand-ecc-strength  : see nand.txt
35- nand-ecc-step-size : see nand.txt
36
37Can support 1-bit HW ECC (default) or if stronger correction is required,
38software-based BCH.
39
40Example:
41
42	fsmc: flash@d1800000 {
43		compatible = "st,spear600-fsmc-nand";
44		#address-cells = <1>;
45		#size-cells = <1>;
46		reg = <0xd1800000 0x1000	/* FSMC Register */
47		       0xd2000000 0x0010	/* NAND Base DATA */
48		       0xd2020000 0x0010	/* NAND Base ADDR */
49		       0xd2010000 0x0010>;	/* NAND Base CMD */
50		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
51
52		bank-width = <1>;
53		nand-skip-bbtscan;
54		timings = /bits/ 8 <0 0 0 2 3 0>;
55		bank = <1>;
56
57		partition@0 {
58			...
59		};
60	};
61