1* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
2
3The Enhanced Secure Digital Host Controller on Freescale i.MX family
4provides an interface for MMC, SD, and SDIO types of memory cards.
5
6This file documents differences between the core properties described
7by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
8
9Required properties:
10- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11	       "fsl,imx25-esdhc"
12	       "fsl,imx35-esdhc"
13	       "fsl,imx51-esdhc"
14	       "fsl,imx53-esdhc"
15	       "fsl,imx6q-usdhc"
16	       "fsl,imx6sl-usdhc"
17	       "fsl,imx6sx-usdhc"
18	       "fsl,imx7d-usdhc"
19
20Optional properties:
21- fsl,wp-controller : Indicate to use controller internal write protection
22- fsl,delay-line : Specify the number of delay cells for override mode.
23  This is used to set the clock delay for DLL(Delay Line) on override mode
24  to select a proper data sampling window in case the clock quality is not good
25  due to signal path is too long on the board. Please refer to eSDHC/uSDHC
26  chapter, DLL (Delay Line) section in RM for details.
27- voltage-ranges : Specify the voltage range in case there are software
28  transparent level shifters on the outputs of the controller. Two cells are
29  required, first cell specifies minimum slot voltage (mV), second cell
30  specifies maximum slot voltage (mV). Several ranges could be specified.
31- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
32  The uSDHC use one delay cell as default increasing step to do tuning process.
33  This property allows user to change the tuning step to more than one delay
34  cells which is useful for some special boards or cards when the default
35  tuning step can't find the proper delay window within limited tuning retries.
36
37Examples:
38
39esdhc@70004000 {
40	compatible = "fsl,imx51-esdhc";
41	reg = <0x70004000 0x4000>;
42	interrupts = <1>;
43	fsl,wp-controller;
44};
45
46esdhc@70008000 {
47	compatible = "fsl,imx51-esdhc";
48	reg = <0x70008000 0x4000>;
49	interrupts = <2>;
50	cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
51	wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
52};
53