1NVIDIA Tegra Memory Controller device tree bindings 2=================================================== 3 4memory-controller node 5---------------------- 6 7Required properties: 8- compatible: Should be "nvidia,tegra<chip>-mc" 9- reg: Physical base address and length of the controller's registers. 10- clocks: Must contain an entry for each entry in clock-names. 11 See ../clocks/clock-bindings.txt for details. 12- clock-names: Must include the following entries: 13 - mc: the module's clock input 14- interrupts: The interrupt outputs from the controller. 15- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines 16 the SWGROUP of the master. 17 18This device implements an IOMMU that complies with the generic IOMMU binding. 19See ../iommu/iommu.txt for details. 20 21emc-timings subnode 22------------------- 23 24The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in 25register PMC_STRAPPING_OPT_A). 26 27Required properties for "emc-timings" nodes : 28- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for. 29 30timing subnode 31-------------- 32 33Each "emc-timings" node should contain a subnode for every supported EMC clock rate. 34 35Required properties for timing nodes : 36- clock-frequency : Should contain the memory clock rate in Hz. 37- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC 38(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be 39specified, according to the board documentation: 40 41 MC_EMEM_ARB_CFG 42 MC_EMEM_ARB_OUTSTANDING_REQ 43 MC_EMEM_ARB_TIMING_RCD 44 MC_EMEM_ARB_TIMING_RP 45 MC_EMEM_ARB_TIMING_RC 46 MC_EMEM_ARB_TIMING_RAS 47 MC_EMEM_ARB_TIMING_FAW 48 MC_EMEM_ARB_TIMING_RRD 49 MC_EMEM_ARB_TIMING_RAP2PRE 50 MC_EMEM_ARB_TIMING_WAP2PRE 51 MC_EMEM_ARB_TIMING_R2R 52 MC_EMEM_ARB_TIMING_W2W 53 MC_EMEM_ARB_TIMING_R2W 54 MC_EMEM_ARB_TIMING_W2R 55 MC_EMEM_ARB_DA_TURNS 56 MC_EMEM_ARB_DA_COVERS 57 MC_EMEM_ARB_MISC0 58 MC_EMEM_ARB_MISC1 59 MC_EMEM_ARB_RING1_THROTTLE 60 61Example SoC include file: 62 63/ { 64 mc: memory-controller@0,70019000 { 65 compatible = "nvidia,tegra124-mc"; 66 reg = <0x0 0x70019000 0x0 0x1000>; 67 clocks = <&tegra_car TEGRA124_CLK_MC>; 68 clock-names = "mc"; 69 70 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 71 72 #iommu-cells = <1>; 73 }; 74 75 sdhci@0,700b0000 { 76 compatible = "nvidia,tegra124-sdhci"; 77 ... 78 iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; 79 }; 80}; 81 82Example board file: 83 84/ { 85 memory-controller@0,70019000 { 86 emc-timings-3 { 87 nvidia,ram-code = <3>; 88 89 timing-12750000 { 90 clock-frequency = <12750000>; 91 92 nvidia,emem-configuration = < 93 0x40040001 /* MC_EMEM_ARB_CFG */ 94 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ 95 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 96 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 97 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 98 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 99 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ 100 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ 101 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ 102 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ 103 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ 104 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ 105 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ 106 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ 107 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ 108 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ 109 0x77e30303 /* MC_EMEM_ARB_MISC0 */ 110 0x70000f03 /* MC_EMEM_ARB_MISC1 */ 111 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ 112 >; 113 }; 114 }; 115 }; 116}; 117