1* Renesas R-Car Display Unit (DU)
2
3Required Properties:
4
5  - compatible: must be one of the following.
6    - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
7    - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
8    - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
9    - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
10    - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
11
12  - reg: A list of base address and length of each memory resource, one for
13    each entry in the reg-names property.
14  - reg-names: Name of the memory resources. The DU requires one memory
15    resource for the DU core (named "du") and one memory resource for each
16    LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
17    index).
18
19  - interrupt-parent: phandle of the parent interrupt controller.
20  - interrupts: Interrupt specifiers for the DU interrupts.
21
22  - clocks: A list of phandles + clock-specifier pairs, one for each entry in
23    the clock-names property.
24  - clock-names: Name of the clocks. This property is model-dependent.
25    - R8A7779 uses a single functional clock. The clock doesn't need to be
26      named.
27    - R8A779[0134] use one functional clock per channel and one clock per LVDS
28      encoder (if available). The functional clocks must be named "du.x" with
29      "x" being the channel numerical index. The LVDS clocks must be named
30      "lvds.x" with "x" being the LVDS encoder numerical index.
31    - In addition to the functional and encoder clocks, all DU versions also
32      support externally supplied pixel clocks. Those clocks are optional.
33      When supplied they must be named "dclkin.x" with "x" being the input
34      clock numerical index.
35
36Required nodes:
37
38The connections to the DU output video ports are modeled using the OF graph
39bindings specified in Documentation/devicetree/bindings/graph.txt.
40
41The following table lists for each supported model the port number
42corresponding to each DU output.
43
44		Port 0		Port1		Port2
45-----------------------------------------------------------------------------
46 R8A7779 (H1)	DPAD 0		DPAD 1		-
47 R8A7790 (H2)	DPAD		LVDS 0		LVDS 1
48 R8A7791 (M2-W)	DPAD		LVDS 0		-
49 R8A7793 (M2-N)	DPAD		LVDS 0		-
50 R8A7794 (E2)	DPAD 0		DPAD 1		-
51
52
53Example: R8A7790 (R-Car H2) DU
54
55	du: du@feb00000 {
56		compatible = "renesas,du-r8a7790";
57		reg = <0 0xfeb00000 0 0x70000>,
58		      <0 0xfeb90000 0 0x1c>,
59		      <0 0xfeb94000 0 0x1c>;
60		reg-names = "du", "lvds.0", "lvds.1";
61		interrupt-parent = <&gic>;
62		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
63			     <0 268 IRQ_TYPE_LEVEL_HIGH>,
64			     <0 269 IRQ_TYPE_LEVEL_HIGH>;
65		clocks = <&mstp7_clks R8A7790_CLK_DU0>,
66		         <&mstp7_clks R8A7790_CLK_DU1>,
67		         <&mstp7_clks R8A7790_CLK_DU2>,
68		         <&mstp7_clks R8A7790_CLK_LVDS0>,
69		         <&mstp7_clks R8A7790_CLK_LVDS1>;
70		clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
71
72		ports {
73			#address-cells = <1>;
74			#size-cells = <0>;
75
76			port@0 {
77				reg = <0>;
78				du_out_rgb: endpoint {
79				};
80			};
81			port@1 {
82				reg = <1>;
83				du_out_lvds0: endpoint {
84				};
85			};
86			port@2 {
87				reg = <2>;
88				du_out_lvds1: endpoint {
89				};
90			};
91		};
92	};
93