1=======================================================
2ARM CCI cache coherent interconnect binding description
3=======================================================
4
5ARM multi-cluster systems maintain intra-cluster coherency through a
6cache coherent interconnect (CCI) that is capable of monitoring bus
7transactions and manage coherency, TLB invalidations and memory barriers.
8
9It allows snooping and distributed virtual memory message broadcast across
10clusters, through memory mapped interface, with a global control register
11space and multiple sets of interface control registers, one per slave
12interface.
13
14Bindings for the CCI node follow the ePAPR standard, available from:
15
16www.power.org/documentation/epapr-version-1-1/
17
18with the addition of the bindings described in this document which are
19specific to ARM.
20
21* CCI interconnect node
22
23	Description: Describes a CCI cache coherent Interconnect component
24
25	Node name must be "cci".
26	Node's parent must be the root node /, and the address space visible
27	through the CCI interconnect is the same as the one seen from the
28	root node (ie from CPUs perspective as per DT standard).
29	Every CCI node has to define the following properties:
30
31	- compatible
32		Usage: required
33		Value type: <string>
34		Definition: must contain one of the following:
35			    "arm,cci-400"
36			    "arm,cci-500"
37
38	- reg
39		Usage: required
40		Value type: Integer cells. A register entry, expressed as a pair
41			    of cells, containing base and size.
42		Definition: A standard property. Specifies base physical
43			    address of CCI control registers common to all
44			    interfaces.
45
46	- ranges:
47		Usage: required
48		Value type: Integer cells. An array of range entries, expressed
49			    as a tuple of cells, containing child address,
50			    parent address and the size of the region in the
51			    child address space.
52		Definition: A standard property. Follow rules in the ePAPR for
53			    hierarchical bus addressing. CCI interfaces
54			    addresses refer to the parent node addressing
55			    scheme to declare their register bases.
56
57	CCI interconnect node can define the following child nodes:
58
59	- CCI control interface nodes
60
61		Node name must be "slave-if".
62		Parent node must be CCI interconnect node.
63
64		A CCI control interface node must contain the following
65		properties:
66
67		- compatible
68			Usage: required
69			Value type: <string>
70			Definition: must be set to
71				    "arm,cci-400-ctrl-if"
72
73		- interface-type:
74			Usage: required
75			Value type: <string>
76			Definition: must be set to one of {"ace", "ace-lite"}
77				    depending on the interface type the node
78				    represents.
79
80		- reg:
81			Usage: required
82			Value type: Integer cells. A register entry, expressed
83				    as a pair of cells, containing base and
84				    size.
85			Definition: the base address and size of the
86				    corresponding interface programming
87				    registers.
88
89	- CCI PMU node
90
91		Parent node must be CCI interconnect node.
92
93		A CCI pmu node must contain the following properties:
94
95		- compatible
96			Usage: required
97			Value type: <string>
98			Definition: Must contain one of:
99				 "arm,cci-400-pmu,r0"
100				 "arm,cci-400-pmu,r1"
101				 "arm,cci-400-pmu"  - DEPRECATED, permitted only where OS has
102						      secure acces to CCI registers
103				 "arm,cci-500-pmu,r0"
104		- reg:
105			Usage: required
106			Value type: Integer cells. A register entry, expressed
107				    as a pair of cells, containing base and
108				    size.
109			Definition: the base address and size of the
110				    corresponding interface programming
111				    registers.
112
113		- interrupts:
114			Usage: required
115			Value type: Integer cells. Array of interrupt specifier
116				    entries, as defined in
117				    ../interrupt-controller/interrupts.txt.
118			Definition: list of counter overflow interrupts, one per
119				    counter. The interrupts must be specified
120				    starting with the cycle counter overflow
121				    interrupt, followed by counter0 overflow
122				    interrupt, counter1 overflow interrupt,...
123				    ,counterN overflow interrupt.
124
125				    The CCI PMU has an interrupt signal for each
126				    counter. The number of interrupts must be
127				    equal to the number of counters.
128
129* CCI interconnect bus masters
130
131	Description: masters in the device tree connected to a CCI port
132		     (inclusive of CPUs and their cpu nodes).
133
134	A CCI interconnect bus master node must contain the following
135	properties:
136
137	- cci-control-port:
138		Usage: required
139		Value type: <phandle>
140		Definition: a phandle containing the CCI control interface node
141			    the master is connected to.
142
143Example:
144
145	cpus {
146		#size-cells = <0>;
147		#address-cells = <1>;
148
149		CPU0: cpu@0 {
150			device_type = "cpu";
151			compatible = "arm,cortex-a15";
152			cci-control-port = <&cci_control1>;
153			reg = <0x0>;
154		};
155
156		CPU1: cpu@1 {
157			device_type = "cpu";
158			compatible = "arm,cortex-a15";
159			cci-control-port = <&cci_control1>;
160			reg = <0x1>;
161		};
162
163		CPU2: cpu@100 {
164			device_type = "cpu";
165			compatible = "arm,cortex-a7";
166			cci-control-port = <&cci_control2>;
167			reg = <0x100>;
168		};
169
170		CPU3: cpu@101 {
171			device_type = "cpu";
172			compatible = "arm,cortex-a7";
173			cci-control-port = <&cci_control2>;
174			reg = <0x101>;
175		};
176
177	};
178
179	dma0: dma@3000000 {
180		compatible = "arm,pl330", "arm,primecell";
181		cci-control-port = <&cci_control0>;
182		reg = <0x0 0x3000000 0x0 0x1000>;
183		interrupts = <10>;
184		#dma-cells = <1>;
185		#dma-channels = <8>;
186		#dma-requests = <32>;
187	};
188
189	cci@2c090000 {
190		compatible = "arm,cci-400";
191		#address-cells = <1>;
192		#size-cells = <1>;
193		reg = <0x0 0x2c090000 0 0x1000>;
194		ranges = <0x0 0x0 0x2c090000 0x10000>;
195
196		cci_control0: slave-if@1000 {
197			compatible = "arm,cci-400-ctrl-if";
198			interface-type = "ace-lite";
199			reg = <0x1000 0x1000>;
200		};
201
202		cci_control1: slave-if@4000 {
203			compatible = "arm,cci-400-ctrl-if";
204			interface-type = "ace";
205			reg = <0x4000 0x1000>;
206		};
207
208		cci_control2: slave-if@5000 {
209			compatible = "arm,cci-400-ctrl-if";
210			interface-type = "ace";
211			reg = <0x5000 0x1000>;
212		};
213
214		pmu@9000 {
215			 compatible = "arm,cci-400-pmu";
216			 reg = <0x9000 0x5000>;
217			 interrupts = <0 101 4>,
218				      <0 102 4>,
219				      <0 103 4>,
220				      <0 104 4>,
221				      <0 105 4>;
222		};
223	};
224
225This CCI node corresponds to a CCI component whose control registers sits
226at address 0x000000002c090000.
227CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
228CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
229CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
230