1/*
2 * fsl_asrc.h - Freescale ASRC ALSA SoC header file
3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 *
6 * Author: Nicolin Chen <nicoleotsuka@gmail.com>
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef _FSL_ASRC_H
14#define _FSL_ASRC_H
15
16#define IN	0
17#define OUT	1
18
19#define ASRC_DMA_BUFFER_NUM		2
20#define ASRC_INPUTFIFO_THRESHOLD	32
21#define ASRC_OUTPUTFIFO_THRESHOLD	32
22#define ASRC_FIFO_THRESHOLD_MIN		0
23#define ASRC_FIFO_THRESHOLD_MAX		63
24#define ASRC_DMA_BUFFER_SIZE		(1024 * 48 * 4)
25#define ASRC_MAX_BUFFER_SIZE		(1024 * 48)
26#define ASRC_OUTPUT_LAST_SAMPLE		8
27
28#define IDEAL_RATIO_RATE		1000000
29
30#define REG_ASRCTR			0x00
31#define REG_ASRIER			0x04
32#define REG_ASRCNCR			0x0C
33#define REG_ASRCFG			0x10
34#define REG_ASRCSR			0x14
35
36#define REG_ASRCDR1			0x18
37#define REG_ASRCDR2			0x1C
38#define REG_ASRCDR(i)			((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
39
40#define REG_ASRSTR			0x20
41#define REG_ASRRA			0x24
42#define REG_ASRRB			0x28
43#define REG_ASRRC			0x2C
44#define REG_ASRPM1			0x40
45#define REG_ASRPM2			0x44
46#define REG_ASRPM3			0x48
47#define REG_ASRPM4			0x4C
48#define REG_ASRPM5			0x50
49#define REG_ASRTFR1			0x54
50#define REG_ASRCCR			0x5C
51
52#define REG_ASRDIA			0x60
53#define REG_ASRDOA			0x64
54#define REG_ASRDIB			0x68
55#define REG_ASRDOB			0x6C
56#define REG_ASRDIC			0x70
57#define REG_ASRDOC			0x74
58#define REG_ASRDI(i)			(REG_ASRDIA + (i << 3))
59#define REG_ASRDO(i)			(REG_ASRDOA + (i << 3))
60#define REG_ASRDx(x, i)			(x == IN ? REG_ASRDI(i) : REG_ASRDO(i))
61
62#define REG_ASRIDRHA			0x80
63#define REG_ASRIDRLA			0x84
64#define REG_ASRIDRHB			0x88
65#define REG_ASRIDRLB			0x8C
66#define REG_ASRIDRHC			0x90
67#define REG_ASRIDRLC			0x94
68#define REG_ASRIDRH(i)			(REG_ASRIDRHA + (i << 3))
69#define REG_ASRIDRL(i)			(REG_ASRIDRLA + (i << 3))
70
71#define REG_ASR76K			0x98
72#define REG_ASR56K			0x9C
73
74#define REG_ASRMCRA			0xA0
75#define REG_ASRFSTA			0xA4
76#define REG_ASRMCRB			0xA8
77#define REG_ASRFSTB			0xAC
78#define REG_ASRMCRC			0xB0
79#define REG_ASRFSTC			0xB4
80#define REG_ASRMCR(i)			(REG_ASRMCRA + (i << 3))
81#define REG_ASRFST(i)			(REG_ASRFSTA + (i << 3))
82
83#define REG_ASRMCR1A			0xC0
84#define REG_ASRMCR1B			0xC4
85#define REG_ASRMCR1C			0xC8
86#define REG_ASRMCR1(i)			(REG_ASRMCR1A + (i << 2))
87
88
89/* REG0 0x00 REG_ASRCTR */
90#define ASRCTR_ATSi_SHIFT(i)		(20 + i)
91#define ASRCTR_ATSi_MASK(i)		(1 << ASRCTR_ATSi_SHIFT(i))
92#define ASRCTR_ATS(i)			(1 << ASRCTR_ATSi_SHIFT(i))
93#define ASRCTR_USRi_SHIFT(i)		(14 + (i << 1))
94#define ASRCTR_USRi_MASK(i)		(1 << ASRCTR_USRi_SHIFT(i))
95#define ASRCTR_USR(i)			(1 << ASRCTR_USRi_SHIFT(i))
96#define ASRCTR_IDRi_SHIFT(i)		(13 + (i << 1))
97#define ASRCTR_IDRi_MASK(i)		(1 << ASRCTR_IDRi_SHIFT(i))
98#define ASRCTR_IDR(i)			(1 << ASRCTR_IDRi_SHIFT(i))
99#define ASRCTR_SRST_SHIFT		4
100#define ASRCTR_SRST_MASK		(1 << ASRCTR_SRST_SHIFT)
101#define ASRCTR_SRST			(1 << ASRCTR_SRST_SHIFT)
102#define ASRCTR_ASRCEi_SHIFT(i)		(1 + i)
103#define ASRCTR_ASRCEi_MASK(i)		(1 << ASRCTR_ASRCEi_SHIFT(i))
104#define ASRCTR_ASRCE(i)			(1 << ASRCTR_ASRCEi_SHIFT(i))
105#define ASRCTR_ASRCEi_ALL_MASK		(0x7 << ASRCTR_ASRCEi_SHIFT(0))
106#define ASRCTR_ASRCEN_SHIFT		0
107#define ASRCTR_ASRCEN_MASK		(1 << ASRCTR_ASRCEN_SHIFT)
108#define ASRCTR_ASRCEN			(1 << ASRCTR_ASRCEN_SHIFT)
109
110/* REG1 0x04 REG_ASRIER */
111#define ASRIER_AFPWE_SHIFT		7
112#define ASRIER_AFPWE_MASK		(1 << ASRIER_AFPWE_SHIFT)
113#define ASRIER_AFPWE			(1 << ASRIER_AFPWE_SHIFT)
114#define ASRIER_AOLIE_SHIFT		6
115#define ASRIER_AOLIE_MASK		(1 << ASRIER_AOLIE_SHIFT)
116#define ASRIER_AOLIE			(1 << ASRIER_AOLIE_SHIFT)
117#define ASRIER_ADOEi_SHIFT(i)		(3 + i)
118#define ASRIER_ADOEi_MASK(i)		(1 << ASRIER_ADOEi_SHIFT(i))
119#define ASRIER_ADOE(i)			(1 << ASRIER_ADOEi_SHIFT(i))
120#define ASRIER_ADIEi_SHIFT(i)		(0 + i)
121#define ASRIER_ADIEi_MASK(i)		(1 << ASRIER_ADIEi_SHIFT(i))
122#define ASRIER_ADIE(i)			(1 << ASRIER_ADIEi_SHIFT(i))
123
124/* REG2 0x0C REG_ASRCNCR */
125#define ASRCNCR_ANCi_SHIFT(i, b)	(b * i)
126#define ASRCNCR_ANCi_MASK(i, b)		(((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
127#define ASRCNCR_ANCi(i, v, b)		((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
128
129/* REG3 0x10 REG_ASRCFG */
130#define ASRCFG_INIRQi_SHIFT(i)		(21 + i)
131#define ASRCFG_INIRQi_MASK(i)		(1 << ASRCFG_INIRQi_SHIFT(i))
132#define ASRCFG_INIRQi			(1 << ASRCFG_INIRQi_SHIFT(i))
133#define ASRCFG_NDPRi_SHIFT(i)		(18 + i)
134#define ASRCFG_NDPRi_MASK(i)		(1 << ASRCFG_NDPRi_SHIFT(i))
135#define ASRCFG_NDPRi			(1 << ASRCFG_NDPRi_SHIFT(i))
136#define ASRCFG_POSTMODi_SHIFT(i)	(8 + (i << 2))
137#define ASRCFG_POSTMODi_WIDTH		2
138#define ASRCFG_POSTMODi_MASK(i)		(((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
139#define ASRCFG_POSTMOD(i, v)		((v) << ASRCFG_POSTMODi_SHIFT(i))
140#define ASRCFG_POSTMODi_UP(i)		(0 << ASRCFG_POSTMODi_SHIFT(i))
141#define ASRCFG_POSTMODi_DCON(i)		(1 << ASRCFG_POSTMODi_SHIFT(i))
142#define ASRCFG_POSTMODi_DOWN(i)		(2 << ASRCFG_POSTMODi_SHIFT(i))
143#define ASRCFG_PREMODi_SHIFT(i)		(6 + (i << 2))
144#define ASRCFG_PREMODi_WIDTH		2
145#define ASRCFG_PREMODi_MASK(i)		(((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
146#define ASRCFG_PREMOD(i, v)		((v) << ASRCFG_PREMODi_SHIFT(i))
147#define ASRCFG_PREMODi_UP(i)		(0 << ASRCFG_PREMODi_SHIFT(i))
148#define ASRCFG_PREMODi_DCON(i)		(1 << ASRCFG_PREMODi_SHIFT(i))
149#define ASRCFG_PREMODi_DOWN(i)		(2 << ASRCFG_PREMODi_SHIFT(i))
150#define ASRCFG_PREMODi_BYPASS(i)	(3 << ASRCFG_PREMODi_SHIFT(i))
151
152/* REG4 0x14 REG_ASRCSR */
153#define ASRCSR_AxCSi_WIDTH		4
154#define ASRCSR_AxCSi_MASK		((1 << ASRCSR_AxCSi_WIDTH) - 1)
155#define ASRCSR_AOCSi_SHIFT(i)		(12 + (i << 2))
156#define ASRCSR_AOCSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
157#define ASRCSR_AOCS(i, v)		((v) << ASRCSR_AOCSi_SHIFT(i))
158#define ASRCSR_AICSi_SHIFT(i)		(i << 2)
159#define ASRCSR_AICSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
160#define ASRCSR_AICS(i, v)		((v) << ASRCSR_AICSi_SHIFT(i))
161
162/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
163#define ASRCDRi_AxCPi_WIDTH		3
164#define ASRCDRi_AICPi_SHIFT(i)		(0 + (i % 2) * 6)
165#define ASRCDRi_AICPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
166#define ASRCDRi_AICP(i, v)		((v) << ASRCDRi_AICPi_SHIFT(i))
167#define ASRCDRi_AICDi_SHIFT(i)		(3 + (i % 2) * 6)
168#define ASRCDRi_AICDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
169#define ASRCDRi_AICD(i, v)		((v) << ASRCDRi_AICDi_SHIFT(i))
170#define ASRCDRi_AOCPi_SHIFT(i)		((i < 2) ? 12 + i * 6 : 6)
171#define ASRCDRi_AOCPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
172#define ASRCDRi_AOCP(i, v)		((v) << ASRCDRi_AOCPi_SHIFT(i))
173#define ASRCDRi_AOCDi_SHIFT(i)		((i < 2) ? 15 + i * 6 : 9)
174#define ASRCDRi_AOCDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
175#define ASRCDRi_AOCD(i, v)		((v) << ASRCDRi_AOCDi_SHIFT(i))
176
177/* REG7 0x20 REG_ASRSTR */
178#define ASRSTR_DSLCNT_SHIFT		21
179#define ASRSTR_DSLCNT_MASK		(1 << ASRSTR_DSLCNT_SHIFT)
180#define ASRSTR_DSLCNT			(1 << ASRSTR_DSLCNT_SHIFT)
181#define ASRSTR_ATQOL_SHIFT		20
182#define ASRSTR_ATQOL_MASK		(1 << ASRSTR_ATQOL_SHIFT)
183#define ASRSTR_ATQOL			(1 << ASRSTR_ATQOL_SHIFT)
184#define ASRSTR_AOOLi_SHIFT(i)		(17 + i)
185#define ASRSTR_AOOLi_MASK(i)		(1 << ASRSTR_AOOLi_SHIFT(i))
186#define ASRSTR_AOOL(i)			(1 << ASRSTR_AOOLi_SHIFT(i))
187#define ASRSTR_AIOLi_SHIFT(i)		(14 + i)
188#define ASRSTR_AIOLi_MASK(i)		(1 << ASRSTR_AIOLi_SHIFT(i))
189#define ASRSTR_AIOL(i)			(1 << ASRSTR_AIOLi_SHIFT(i))
190#define ASRSTR_AODOi_SHIFT(i)		(11 + i)
191#define ASRSTR_AODOi_MASK(i)		(1 << ASRSTR_AODOi_SHIFT(i))
192#define ASRSTR_AODO(i)			(1 << ASRSTR_AODOi_SHIFT(i))
193#define ASRSTR_AIDUi_SHIFT(i)		(8 + i)
194#define ASRSTR_AIDUi_MASK(i)		(1 << ASRSTR_AIDUi_SHIFT(i))
195#define ASRSTR_AIDU(i)			(1 << ASRSTR_AIDUi_SHIFT(i))
196#define ASRSTR_FPWT_SHIFT		7
197#define ASRSTR_FPWT_MASK		(1 << ASRSTR_FPWT_SHIFT)
198#define ASRSTR_FPWT			(1 << ASRSTR_FPWT_SHIFT)
199#define ASRSTR_AOLE_SHIFT		6
200#define ASRSTR_AOLE_MASK		(1 << ASRSTR_AOLE_SHIFT)
201#define ASRSTR_AOLE			(1 << ASRSTR_AOLE_SHIFT)
202#define ASRSTR_AODEi_SHIFT(i)		(3 + i)
203#define ASRSTR_AODFi_MASK(i)		(1 << ASRSTR_AODEi_SHIFT(i))
204#define ASRSTR_AODF(i)			(1 << ASRSTR_AODEi_SHIFT(i))
205#define ASRSTR_AIDEi_SHIFT(i)		(0 + i)
206#define ASRSTR_AIDEi_MASK(i)		(1 << ASRSTR_AIDEi_SHIFT(i))
207#define ASRSTR_AIDE(i)			(1 << ASRSTR_AIDEi_SHIFT(i))
208
209/* REG10 0x54 REG_ASRTFR1 */
210#define ASRTFR1_TF_BASE_WIDTH		7
211#define ASRTFR1_TF_BASE_SHIFT		6
212#define ASRTFR1_TF_BASE_MASK		(((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
213#define ASRTFR1_TF_BASE(i)		((i) << ASRTFR1_TF_BASE_SHIFT)
214
215/*
216 * REG22 0xA0 REG_ASRMCRA
217 * REG24 0xA8 REG_ASRMCRB
218 * REG26 0xB0 REG_ASRMCRC
219 */
220#define ASRMCRi_ZEROBUFi_SHIFT		23
221#define ASRMCRi_ZEROBUFi_MASK		(1 << ASRMCRi_ZEROBUFi_SHIFT)
222#define ASRMCRi_ZEROBUFi		(1 << ASRMCRi_ZEROBUFi_SHIFT)
223#define ASRMCRi_EXTTHRSHi_SHIFT		22
224#define ASRMCRi_EXTTHRSHi_MASK		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
225#define ASRMCRi_EXTTHRSHi		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
226#define ASRMCRi_BUFSTALLi_SHIFT		21
227#define ASRMCRi_BUFSTALLi_MASK		(1 << ASRMCRi_BUFSTALLi_SHIFT)
228#define ASRMCRi_BUFSTALLi		(1 << ASRMCRi_BUFSTALLi_SHIFT)
229#define ASRMCRi_BYPASSPOLYi_SHIFT	20
230#define ASRMCRi_BYPASSPOLYi_MASK	(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
231#define ASRMCRi_BYPASSPOLYi		(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
232#define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH	6
233#define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT	12
234#define ASRMCRi_OUTFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
235#define ASRMCRi_OUTFIFO_THRESHOLD(v)	(((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
236#define ASRMCRi_RSYNIFi_SHIFT		11
237#define ASRMCRi_RSYNIFi_MASK		(1 << ASRMCRi_RSYNIFi_SHIFT)
238#define ASRMCRi_RSYNIFi			(1 << ASRMCRi_RSYNIFi_SHIFT)
239#define ASRMCRi_RSYNOFi_SHIFT		10
240#define ASRMCRi_RSYNOFi_MASK		(1 << ASRMCRi_RSYNOFi_SHIFT)
241#define ASRMCRi_RSYNOFi			(1 << ASRMCRi_RSYNOFi_SHIFT)
242#define ASRMCRi_INFIFO_THRESHOLD_WIDTH	6
243#define ASRMCRi_INFIFO_THRESHOLD_SHIFT	0
244#define ASRMCRi_INFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
245#define ASRMCRi_INFIFO_THRESHOLD(v)	(((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
246
247/*
248 * REG23 0xA4 REG_ASRFSTA
249 * REG25 0xAC REG_ASRFSTB
250 * REG27 0xB4 REG_ASRFSTC
251 */
252#define ASRFSTi_OAFi_SHIFT		23
253#define ASRFSTi_OAFi_MASK		(1 << ASRFSTi_OAFi_SHIFT)
254#define ASRFSTi_OAFi			(1 << ASRFSTi_OAFi_SHIFT)
255#define ASRFSTi_OUTPUT_FIFO_WIDTH	7
256#define ASRFSTi_OUTPUT_FIFO_SHIFT	12
257#define ASRFSTi_OUTPUT_FIFO_MASK	(((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
258#define ASRFSTi_IAEi_SHIFT		11
259#define ASRFSTi_IAEi_MASK		(1 << ASRFSTi_OAFi_SHIFT)
260#define ASRFSTi_IAEi			(1 << ASRFSTi_OAFi_SHIFT)
261#define ASRFSTi_INPUT_FIFO_WIDTH	7
262#define ASRFSTi_INPUT_FIFO_SHIFT	0
263#define ASRFSTi_INPUT_FIFO_MASK		((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
264
265/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
266#define ASRMCR1i_IWD_WIDTH		3
267#define ASRMCR1i_IWD_SHIFT		9
268#define ASRMCR1i_IWD_MASK		(((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
269#define ASRMCR1i_IWD(v)			((v) << ASRMCR1i_IWD_SHIFT)
270#define ASRMCR1i_IMSB_SHIFT		8
271#define ASRMCR1i_IMSB_MASK		(1 << ASRMCR1i_IMSB_SHIFT)
272#define ASRMCR1i_IMSB_MSB		(1 << ASRMCR1i_IMSB_SHIFT)
273#define ASRMCR1i_IMSB_LSB		(0 << ASRMCR1i_IMSB_SHIFT)
274#define ASRMCR1i_OMSB_SHIFT		2
275#define ASRMCR1i_OMSB_MASK		(1 << ASRMCR1i_OMSB_SHIFT)
276#define ASRMCR1i_OMSB_MSB		(1 << ASRMCR1i_OMSB_SHIFT)
277#define ASRMCR1i_OMSB_LSB		(0 << ASRMCR1i_OMSB_SHIFT)
278#define ASRMCR1i_OSGN_SHIFT		1
279#define ASRMCR1i_OSGN_MASK		(1 << ASRMCR1i_OSGN_SHIFT)
280#define ASRMCR1i_OSGN			(1 << ASRMCR1i_OSGN_SHIFT)
281#define ASRMCR1i_OW16_SHIFT		0
282#define ASRMCR1i_OW16_MASK		(1 << ASRMCR1i_OW16_SHIFT)
283#define ASRMCR1i_OW16(v)		((v) << ASRMCR1i_OW16_SHIFT)
284
285
286enum asrc_pair_index {
287	ASRC_INVALID_PAIR = -1,
288	ASRC_PAIR_A = 0,
289	ASRC_PAIR_B = 1,
290	ASRC_PAIR_C = 2,
291};
292
293#define ASRC_PAIR_MAX_NUM	(ASRC_PAIR_C + 1)
294
295enum asrc_inclk {
296	INCLK_NONE = 0x03,
297	INCLK_ESAI_RX = 0x00,
298	INCLK_SSI1_RX = 0x01,
299	INCLK_SSI2_RX = 0x02,
300	INCLK_SSI3_RX = 0x07,
301	INCLK_SPDIF_RX = 0x04,
302	INCLK_MLB_CLK = 0x05,
303	INCLK_PAD = 0x06,
304	INCLK_ESAI_TX = 0x08,
305	INCLK_SSI1_TX = 0x09,
306	INCLK_SSI2_TX = 0x0a,
307	INCLK_SSI3_TX = 0x0b,
308	INCLK_SPDIF_TX = 0x0c,
309	INCLK_ASRCK1_CLK = 0x0f,
310};
311
312enum asrc_outclk {
313	OUTCLK_NONE = 0x03,
314	OUTCLK_ESAI_TX = 0x00,
315	OUTCLK_SSI1_TX = 0x01,
316	OUTCLK_SSI2_TX = 0x02,
317	OUTCLK_SSI3_TX = 0x07,
318	OUTCLK_SPDIF_TX = 0x04,
319	OUTCLK_MLB_CLK = 0x05,
320	OUTCLK_PAD = 0x06,
321	OUTCLK_ESAI_RX = 0x08,
322	OUTCLK_SSI1_RX = 0x09,
323	OUTCLK_SSI2_RX = 0x0a,
324	OUTCLK_SSI3_RX = 0x0b,
325	OUTCLK_SPDIF_RX = 0x0c,
326	OUTCLK_ASRCK1_CLK = 0x0f,
327};
328
329#define ASRC_CLK_MAX_NUM	16
330
331enum asrc_word_width {
332	ASRC_WIDTH_24_BIT = 0,
333	ASRC_WIDTH_16_BIT = 1,
334	ASRC_WIDTH_8_BIT = 2,
335};
336
337struct asrc_config {
338	enum asrc_pair_index pair;
339	unsigned int channel_num;
340	unsigned int buffer_num;
341	unsigned int dma_buffer_size;
342	unsigned int input_sample_rate;
343	unsigned int output_sample_rate;
344	enum asrc_word_width input_word_width;
345	enum asrc_word_width output_word_width;
346	enum asrc_inclk inclk;
347	enum asrc_outclk outclk;
348};
349
350struct asrc_req {
351	unsigned int chn_num;
352	enum asrc_pair_index index;
353};
354
355struct asrc_querybuf {
356	unsigned int buffer_index;
357	unsigned int input_length;
358	unsigned int output_length;
359	unsigned long input_offset;
360	unsigned long output_offset;
361};
362
363struct asrc_convert_buffer {
364	void *input_buffer_vaddr;
365	void *output_buffer_vaddr;
366	unsigned int input_buffer_length;
367	unsigned int output_buffer_length;
368};
369
370struct asrc_status_flags {
371	enum asrc_pair_index index;
372	unsigned int overload_error;
373};
374
375enum asrc_error_status {
376	ASRC_TASK_Q_OVERLOAD		= 0x01,
377	ASRC_OUTPUT_TASK_OVERLOAD	= 0x02,
378	ASRC_INPUT_TASK_OVERLOAD	= 0x04,
379	ASRC_OUTPUT_BUFFER_OVERFLOW	= 0x08,
380	ASRC_INPUT_BUFFER_UNDERRUN	= 0x10,
381};
382
383struct dma_block {
384	dma_addr_t dma_paddr;
385	void *dma_vaddr;
386	unsigned int length;
387};
388
389/**
390 * fsl_asrc_pair: ASRC Pair private data
391 *
392 * @asrc_priv: pointer to its parent module
393 * @config: configuration profile
394 * @error: error record
395 * @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C)
396 * @channels: occupied channel number
397 * @desc: input and output dma descriptors
398 * @dma_chan: inputer and output DMA channels
399 * @dma_data: private dma data
400 * @pos: hardware pointer position
401 * @private: pair private area
402 */
403struct fsl_asrc_pair {
404	struct fsl_asrc *asrc_priv;
405	struct asrc_config *config;
406	unsigned int error;
407
408	enum asrc_pair_index index;
409	unsigned int channels;
410
411	struct dma_async_tx_descriptor *desc[2];
412	struct dma_chan *dma_chan[2];
413	struct imx_dma_data dma_data;
414	unsigned int pos;
415
416	void *private;
417};
418
419/**
420 * fsl_asrc_pair: ASRC private data
421 *
422 * @dma_params_rx: DMA parameters for receive channel
423 * @dma_params_tx: DMA parameters for transmit channel
424 * @pdev: platform device pointer
425 * @regmap: regmap handler
426 * @paddr: physical address to the base address of registers
427 * @mem_clk: clock source to access register
428 * @ipg_clk: clock source to drive peripheral
429 * @asrck_clk: clock sources to driver ASRC internal logic
430 * @lock: spin lock for resource protection
431 * @pair: pair pointers
432 * @channel_bits: width of ASRCNCR register for each pair
433 * @channel_avail: non-occupied channel numbers
434 * @asrc_rate: default sample rate for ASoC Back-Ends
435 * @asrc_width: default sample width for ASoC Back-Ends
436 */
437struct fsl_asrc {
438	struct snd_dmaengine_dai_dma_data dma_params_rx;
439	struct snd_dmaengine_dai_dma_data dma_params_tx;
440	struct platform_device *pdev;
441	struct regmap *regmap;
442	unsigned long paddr;
443	struct clk *mem_clk;
444	struct clk *ipg_clk;
445	struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
446	spinlock_t lock;
447
448	struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM];
449	unsigned int channel_bits;
450	unsigned int channel_avail;
451
452	int asrc_rate;
453	int asrc_width;
454};
455
456extern struct snd_soc_platform_driver fsl_asrc_platform;
457struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir);
458#endif /* _FSL_ASRC_H */
459