1/* 2 * wm8991.c -- WM8991 ALSA Soc Audio driver 3 * 4 * Copyright 2007-2010 Wolfson Microelectronics PLC. 5 * Author: Graeme Gregory 6 * Graeme.Gregory@wolfsonmicro.com 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/kernel.h> 17#include <linux/init.h> 18#include <linux/delay.h> 19#include <linux/pm.h> 20#include <linux/i2c.h> 21#include <linux/regmap.h> 22#include <linux/slab.h> 23#include <sound/core.h> 24#include <sound/pcm.h> 25#include <sound/pcm_params.h> 26#include <sound/soc.h> 27#include <sound/soc-dapm.h> 28#include <sound/initval.h> 29#include <sound/tlv.h> 30#include <asm/div64.h> 31 32#include "wm8991.h" 33 34struct wm8991_priv { 35 struct regmap *regmap; 36 unsigned int pcmclk; 37}; 38 39static const struct reg_default wm8991_reg_defaults[] = { 40 { 1, 0x0000 }, /* R1 - Power Management (1) */ 41 { 2, 0x6000 }, /* R2 - Power Management (2) */ 42 { 3, 0x0000 }, /* R3 - Power Management (3) */ 43 { 4, 0x4050 }, /* R4 - Audio Interface (1) */ 44 { 5, 0x4000 }, /* R5 - Audio Interface (2) */ 45 { 6, 0x01C8 }, /* R6 - Clocking (1) */ 46 { 7, 0x0000 }, /* R7 - Clocking (2) */ 47 { 8, 0x0040 }, /* R8 - Audio Interface (3) */ 48 { 9, 0x0040 }, /* R9 - Audio Interface (4) */ 49 { 10, 0x0004 }, /* R10 - DAC CTRL */ 50 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ 51 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ 52 { 13, 0x0000 }, /* R13 - Digital Side Tone */ 53 { 14, 0x0100 }, /* R14 - ADC CTRL */ 54 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ 55 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ 56 57 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ 58 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */ 59 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */ 60 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */ 61 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ 62 { 23, 0x0800 }, /* R23 - GPIO_POL */ 63 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ 64 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ 65 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ 66 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ 67 { 28, 0x0000 }, /* R28 - Left Output Volume */ 68 { 29, 0x0000 }, /* R29 - Right Output Volume */ 69 { 30, 0x0066 }, /* R30 - Line Outputs Volume */ 70 { 31, 0x0022 }, /* R31 - Out3/4 Volume */ 71 { 32, 0x0079 }, /* R32 - Left OPGA Volume */ 72 { 33, 0x0079 }, /* R33 - Right OPGA Volume */ 73 { 34, 0x0003 }, /* R34 - Speaker Volume */ 74 { 35, 0x0003 }, /* R35 - ClassD1 */ 75 76 { 37, 0x0100 }, /* R37 - ClassD3 */ 77 78 { 39, 0x0000 }, /* R39 - Input Mixer1 */ 79 { 40, 0x0000 }, /* R40 - Input Mixer2 */ 80 { 41, 0x0000 }, /* R41 - Input Mixer3 */ 81 { 42, 0x0000 }, /* R42 - Input Mixer4 */ 82 { 43, 0x0000 }, /* R43 - Input Mixer5 */ 83 { 44, 0x0000 }, /* R44 - Input Mixer6 */ 84 { 45, 0x0000 }, /* R45 - Output Mixer1 */ 85 { 46, 0x0000 }, /* R46 - Output Mixer2 */ 86 { 47, 0x0000 }, /* R47 - Output Mixer3 */ 87 { 48, 0x0000 }, /* R48 - Output Mixer4 */ 88 { 49, 0x0000 }, /* R49 - Output Mixer5 */ 89 { 50, 0x0000 }, /* R50 - Output Mixer6 */ 90 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */ 91 { 52, 0x0000 }, /* R52 - Line Mixer1 */ 92 { 53, 0x0000 }, /* R53 - Line Mixer2 */ 93 { 54, 0x0000 }, /* R54 - Speaker Mixer */ 94 { 55, 0x0000 }, /* R55 - Additional Control */ 95 { 56, 0x0000 }, /* R56 - AntiPOP1 */ 96 { 57, 0x0000 }, /* R57 - AntiPOP2 */ 97 { 58, 0x0000 }, /* R58 - MICBIAS */ 98 99 { 60, 0x0008 }, /* R60 - PLL1 */ 100 { 61, 0x0031 }, /* R61 - PLL2 */ 101 { 62, 0x0026 }, /* R62 - PLL3 */ 102}; 103 104static bool wm8991_volatile(struct device *dev, unsigned int reg) 105{ 106 switch (reg) { 107 case WM8991_RESET: 108 return true; 109 default: 110 return false; 111 } 112} 113 114static const unsigned int rec_mix_tlv[] = { 115 TLV_DB_RANGE_HEAD(1), 116 0, 7, TLV_DB_LINEAR_ITEM(-1500, 600), 117}; 118 119static const unsigned int in_pga_tlv[] = { 120 TLV_DB_RANGE_HEAD(1), 121 0, 0x1F, TLV_DB_LINEAR_ITEM(-1650, 3000), 122}; 123 124static const unsigned int out_mix_tlv[] = { 125 TLV_DB_RANGE_HEAD(1), 126 0, 7, TLV_DB_LINEAR_ITEM(0, -2100), 127}; 128 129static const unsigned int out_pga_tlv[] = { 130 TLV_DB_RANGE_HEAD(1), 131 0, 127, TLV_DB_LINEAR_ITEM(-7300, 600), 132}; 133 134static const unsigned int out_omix_tlv[] = { 135 TLV_DB_RANGE_HEAD(1), 136 0, 7, TLV_DB_LINEAR_ITEM(-600, 0), 137}; 138 139static const unsigned int out_dac_tlv[] = { 140 TLV_DB_RANGE_HEAD(1), 141 0, 255, TLV_DB_LINEAR_ITEM(-7163, 0), 142}; 143 144static const unsigned int in_adc_tlv[] = { 145 TLV_DB_RANGE_HEAD(1), 146 0, 255, TLV_DB_LINEAR_ITEM(-7163, 1763), 147}; 148 149static const unsigned int out_sidetone_tlv[] = { 150 TLV_DB_RANGE_HEAD(1), 151 0, 31, TLV_DB_LINEAR_ITEM(-3600, 0), 152}; 153 154static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 155 struct snd_ctl_elem_value *ucontrol) 156{ 157 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 158 int reg = kcontrol->private_value & 0xff; 159 int ret; 160 u16 val; 161 162 ret = snd_soc_put_volsw(kcontrol, ucontrol); 163 if (ret < 0) 164 return ret; 165 166 /* now hit the volume update bits (always bit 8) */ 167 val = snd_soc_read(codec, reg); 168 return snd_soc_write(codec, reg, val | 0x0100); 169} 170 171static const char *wm8991_digital_sidetone[] = 172{"None", "Left ADC", "Right ADC", "Reserved"}; 173 174static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum, 175 WM8991_DIGITAL_SIDE_TONE, 176 WM8991_ADC_TO_DACL_SHIFT, 177 wm8991_digital_sidetone); 178 179static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum, 180 WM8991_DIGITAL_SIDE_TONE, 181 WM8991_ADC_TO_DACR_SHIFT, 182 wm8991_digital_sidetone); 183 184static const char *wm8991_adcmode[] = 185{"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; 186 187static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum, 188 WM8991_ADC_CTRL, 189 WM8991_ADC_HPF_CUT_SHIFT, 190 wm8991_adcmode); 191 192static const struct snd_kcontrol_new wm8991_snd_controls[] = { 193 /* INMIXL */ 194 SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0), 195 SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0), 196 /* INMIXR */ 197 SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0), 198 SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0), 199 200 /* LOMIX */ 201 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3, 202 WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv), 203 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, 204 WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv), 205 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, 206 WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv), 207 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5, 208 WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv), 209 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5, 210 WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), 211 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5, 212 WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), 213 214 /* ROMIX */ 215 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4, 216 WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv), 217 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, 218 WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv), 219 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, 220 WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv), 221 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6, 222 WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv), 223 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6, 224 WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv), 225 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6, 226 WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv), 227 228 /* LOUT */ 229 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME, 230 WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv), 231 SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0), 232 233 /* ROUT */ 234 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME, 235 WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv), 236 SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0), 237 238 /* LOPGA */ 239 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME, 240 WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv), 241 SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME, 242 WM8991_LOPGAZC_BIT, 1, 0), 243 244 /* ROPGA */ 245 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME, 246 WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv), 247 SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME, 248 WM8991_ROPGAZC_BIT, 1, 0), 249 250 SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 251 WM8991_LONMUTE_BIT, 1, 0), 252 SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 253 WM8991_LOPMUTE_BIT, 1, 0), 254 SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, 255 WM8991_LOATTN_BIT, 1, 0), 256 SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 257 WM8991_RONMUTE_BIT, 1, 0), 258 SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, 259 WM8991_ROPMUTE_BIT, 1, 0), 260 SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, 261 WM8991_ROATTN_BIT, 1, 0), 262 263 SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME, 264 WM8991_OUT3MUTE_BIT, 1, 0), 265 SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME, 266 WM8991_OUT3ATTN_BIT, 1, 0), 267 268 SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME, 269 WM8991_OUT4MUTE_BIT, 1, 0), 270 SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME, 271 WM8991_OUT4ATTN_BIT, 1, 0), 272 273 SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1, 274 WM8991_CDMODE_BIT, 1, 0), 275 276 SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME, 277 WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0), 278 SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3, 279 WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0), 280 SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3, 281 WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0), 282 283 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", 284 WM8991_LEFT_DAC_DIGITAL_VOLUME, 285 WM8991_DACL_VOL_SHIFT, 286 WM8991_DACL_VOL_MASK, 287 0, 288 out_dac_tlv), 289 290 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", 291 WM8991_RIGHT_DAC_DIGITAL_VOLUME, 292 WM8991_DACR_VOL_SHIFT, 293 WM8991_DACR_VOL_MASK, 294 0, 295 out_dac_tlv), 296 297 SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum), 298 SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum), 299 300 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, 301 WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0, 302 out_sidetone_tlv), 303 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, 304 WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0, 305 out_sidetone_tlv), 306 307 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL, 308 WM8991_ADC_HPF_ENA_BIT, 1, 0), 309 310 SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum), 311 312 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", 313 WM8991_LEFT_ADC_DIGITAL_VOLUME, 314 WM8991_ADCL_VOL_SHIFT, 315 WM8991_ADCL_VOL_MASK, 316 0, 317 in_adc_tlv), 318 319 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", 320 WM8991_RIGHT_ADC_DIGITAL_VOLUME, 321 WM8991_ADCR_VOL_SHIFT, 322 WM8991_ADCR_VOL_MASK, 323 0, 324 in_adc_tlv), 325 326 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", 327 WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 328 WM8991_LIN12VOL_SHIFT, 329 WM8991_LIN12VOL_MASK, 330 0, 331 in_pga_tlv), 332 333 SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 334 WM8991_LI12ZC_BIT, 1, 0), 335 336 SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, 337 WM8991_LI12MUTE_BIT, 1, 0), 338 339 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", 340 WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 341 WM8991_LIN34VOL_SHIFT, 342 WM8991_LIN34VOL_MASK, 343 0, 344 in_pga_tlv), 345 346 SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 347 WM8991_LI34ZC_BIT, 1, 0), 348 349 SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, 350 WM8991_LI34MUTE_BIT, 1, 0), 351 352 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", 353 WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 354 WM8991_RIN12VOL_SHIFT, 355 WM8991_RIN12VOL_MASK, 356 0, 357 in_pga_tlv), 358 359 SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 360 WM8991_RI12ZC_BIT, 1, 0), 361 362 SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, 363 WM8991_RI12MUTE_BIT, 1, 0), 364 365 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", 366 WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 367 WM8991_RIN34VOL_SHIFT, 368 WM8991_RIN34VOL_MASK, 369 0, 370 in_pga_tlv), 371 372 SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 373 WM8991_RI34ZC_BIT, 1, 0), 374 375 SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, 376 WM8991_RI34MUTE_BIT, 1, 0), 377}; 378 379/* 380 * _DAPM_ Controls 381 */ 382static int outmixer_event(struct snd_soc_dapm_widget *w, 383 struct snd_kcontrol *kcontrol, int event) 384{ 385 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 386 u32 reg_shift = kcontrol->private_value & 0xfff; 387 int ret = 0; 388 u16 reg; 389 390 switch (reg_shift) { 391 case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8): 392 reg = snd_soc_read(codec, WM8991_OUTPUT_MIXER1); 393 if (reg & WM8991_LDLO) { 394 printk(KERN_WARNING 395 "Cannot set as Output Mixer 1 LDLO Set\n"); 396 ret = -1; 397 } 398 break; 399 400 case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8): 401 reg = snd_soc_read(codec, WM8991_OUTPUT_MIXER2); 402 if (reg & WM8991_RDRO) { 403 printk(KERN_WARNING 404 "Cannot set as Output Mixer 2 RDRO Set\n"); 405 ret = -1; 406 } 407 break; 408 409 case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8): 410 reg = snd_soc_read(codec, WM8991_SPEAKER_MIXER); 411 if (reg & WM8991_LDSPK) { 412 printk(KERN_WARNING 413 "Cannot set as Speaker Mixer LDSPK Set\n"); 414 ret = -1; 415 } 416 break; 417 418 case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8): 419 reg = snd_soc_read(codec, WM8991_SPEAKER_MIXER); 420 if (reg & WM8991_RDSPK) { 421 printk(KERN_WARNING 422 "Cannot set as Speaker Mixer RDSPK Set\n"); 423 ret = -1; 424 } 425 break; 426 } 427 428 return ret; 429} 430 431/* INMIX dB values */ 432static const unsigned int in_mix_tlv[] = { 433 TLV_DB_RANGE_HEAD(1), 434 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600), 435}; 436 437/* Left In PGA Connections */ 438static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = { 439 SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0), 440 SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0), 441}; 442 443static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = { 444 SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0), 445 SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0), 446}; 447 448/* Right In PGA Connections */ 449static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = { 450 SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0), 451 SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0), 452}; 453 454static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = { 455 SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0), 456 SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0), 457}; 458 459/* INMIXL */ 460static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = { 461 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3, 462 WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv), 463 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT, 464 7, 0, in_mix_tlv), 465 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, 466 1, 0), 467 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, 468 1, 0), 469}; 470 471/* INMIXR */ 472static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = { 473 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4, 474 WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv), 475 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT, 476 7, 0, in_mix_tlv), 477 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, 478 1, 0), 479 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, 480 1, 0), 481}; 482 483/* AINLMUX */ 484static const char *wm8991_ainlmux[] = 485{"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; 486 487static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum, 488 WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT, 489 wm8991_ainlmux); 490 491static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls = 492 SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum); 493 494/* DIFFINL */ 495 496/* AINRMUX */ 497static const char *wm8991_ainrmux[] = 498{"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; 499 500static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum, 501 WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT, 502 wm8991_ainrmux); 503 504static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls = 505 SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum); 506 507/* RXVOICE */ 508static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = { 509 SOC_DAPM_SINGLE_TLV("LIN4RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT, 510 WM8991_LR4BVOL_MASK, 0, in_mix_tlv), 511 SOC_DAPM_SINGLE_TLV("RIN4RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT, 512 WM8991_RL4BVOL_MASK, 0, in_mix_tlv), 513}; 514 515/* LOMIX */ 516static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = { 517 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1, 518 WM8991_LRBLO_BIT, 1, 0), 519 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1, 520 WM8991_LLBLO_BIT, 1, 0), 521 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, 522 WM8991_LRI3LO_BIT, 1, 0), 523 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, 524 WM8991_LLI3LO_BIT, 1, 0), 525 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, 526 WM8991_LR12LO_BIT, 1, 0), 527 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, 528 WM8991_LL12LO_BIT, 1, 0), 529 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1, 530 WM8991_LDLO_BIT, 1, 0), 531}; 532 533/* ROMIX */ 534static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = { 535 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2, 536 WM8991_RLBRO_BIT, 1, 0), 537 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2, 538 WM8991_RRBRO_BIT, 1, 0), 539 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, 540 WM8991_RLI3RO_BIT, 1, 0), 541 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, 542 WM8991_RRI3RO_BIT, 1, 0), 543 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, 544 WM8991_RL12RO_BIT, 1, 0), 545 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, 546 WM8991_RR12RO_BIT, 1, 0), 547 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2, 548 WM8991_RDRO_BIT, 1, 0), 549}; 550 551/* LONMIX */ 552static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = { 553 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, 554 WM8991_LLOPGALON_BIT, 1, 0), 555 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1, 556 WM8991_LROPGALON_BIT, 1, 0), 557 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1, 558 WM8991_LOPLON_BIT, 1, 0), 559}; 560 561/* LOPMIX */ 562static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = { 563 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1, 564 WM8991_LR12LOP_BIT, 1, 0), 565 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1, 566 WM8991_LL12LOP_BIT, 1, 0), 567 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, 568 WM8991_LLOPGALOP_BIT, 1, 0), 569}; 570 571/* RONMIX */ 572static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = { 573 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, 574 WM8991_RROPGARON_BIT, 1, 0), 575 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2, 576 WM8991_RLOPGARON_BIT, 1, 0), 577 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2, 578 WM8991_ROPRON_BIT, 1, 0), 579}; 580 581/* ROPMIX */ 582static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = { 583 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2, 584 WM8991_RL12ROP_BIT, 1, 0), 585 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2, 586 WM8991_RR12ROP_BIT, 1, 0), 587 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, 588 WM8991_RROPGAROP_BIT, 1, 0), 589}; 590 591/* OUT3MIX */ 592static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = { 593 SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER, 594 WM8991_LI4O3_BIT, 1, 0), 595 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER, 596 WM8991_LPGAO3_BIT, 1, 0), 597}; 598 599/* OUT4MIX */ 600static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = { 601 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER, 602 WM8991_RPGAO4_BIT, 1, 0), 603 SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER, 604 WM8991_RI4O4_BIT, 1, 0), 605}; 606 607/* SPKMIX */ 608static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = { 609 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER, 610 WM8991_LI2SPK_BIT, 1, 0), 611 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER, 612 WM8991_LB2SPK_BIT, 1, 0), 613 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER, 614 WM8991_LOPGASPK_BIT, 1, 0), 615 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER, 616 WM8991_LDSPK_BIT, 1, 0), 617 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER, 618 WM8991_RDSPK_BIT, 1, 0), 619 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER, 620 WM8991_ROPGASPK_BIT, 1, 0), 621 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER, 622 WM8991_RL12ROP_BIT, 1, 0), 623 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER, 624 WM8991_RI2SPK_BIT, 1, 0), 625}; 626 627static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = { 628 /* Input Side */ 629 /* Input Lines */ 630 SND_SOC_DAPM_INPUT("LIN1"), 631 SND_SOC_DAPM_INPUT("LIN2"), 632 SND_SOC_DAPM_INPUT("LIN3"), 633 SND_SOC_DAPM_INPUT("LIN4RXN"), 634 SND_SOC_DAPM_INPUT("RIN3"), 635 SND_SOC_DAPM_INPUT("RIN4RXP"), 636 SND_SOC_DAPM_INPUT("RIN1"), 637 SND_SOC_DAPM_INPUT("RIN2"), 638 SND_SOC_DAPM_INPUT("Internal ADC Source"), 639 640 SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2, 641 WM8991_AINL_ENA_BIT, 0, NULL, 0), 642 SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2, 643 WM8991_AINR_ENA_BIT, 0, NULL, 0), 644 645 /* DACs */ 646 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2, 647 WM8991_ADCL_ENA_BIT, 0), 648 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2, 649 WM8991_ADCR_ENA_BIT, 0), 650 651 /* Input PGAs */ 652 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT, 653 0, &wm8991_dapm_lin12_pga_controls[0], 654 ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)), 655 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT, 656 0, &wm8991_dapm_lin34_pga_controls[0], 657 ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)), 658 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT, 659 0, &wm8991_dapm_rin12_pga_controls[0], 660 ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)), 661 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT, 662 0, &wm8991_dapm_rin34_pga_controls[0], 663 ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)), 664 665 /* INMIXL */ 666 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0, 667 &wm8991_dapm_inmixl_controls[0], 668 ARRAY_SIZE(wm8991_dapm_inmixl_controls)), 669 670 /* AINLMUX */ 671 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, 672 &wm8991_dapm_ainlmux_controls), 673 674 /* INMIXR */ 675 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0, 676 &wm8991_dapm_inmixr_controls[0], 677 ARRAY_SIZE(wm8991_dapm_inmixr_controls)), 678 679 /* AINRMUX */ 680 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, 681 &wm8991_dapm_ainrmux_controls), 682 683 /* Output Side */ 684 /* DACs */ 685 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3, 686 WM8991_DACL_ENA_BIT, 0), 687 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3, 688 WM8991_DACR_ENA_BIT, 0), 689 690 /* LOMIX */ 691 SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT, 692 0, &wm8991_dapm_lomix_controls[0], 693 ARRAY_SIZE(wm8991_dapm_lomix_controls), 694 outmixer_event, SND_SOC_DAPM_PRE_REG), 695 696 /* LONMIX */ 697 SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0, 698 &wm8991_dapm_lonmix_controls[0], 699 ARRAY_SIZE(wm8991_dapm_lonmix_controls)), 700 701 /* LOPMIX */ 702 SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0, 703 &wm8991_dapm_lopmix_controls[0], 704 ARRAY_SIZE(wm8991_dapm_lopmix_controls)), 705 706 /* OUT3MIX */ 707 SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0, 708 &wm8991_dapm_out3mix_controls[0], 709 ARRAY_SIZE(wm8991_dapm_out3mix_controls)), 710 711 /* SPKMIX */ 712 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0, 713 &wm8991_dapm_spkmix_controls[0], 714 ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event, 715 SND_SOC_DAPM_PRE_REG), 716 717 /* OUT4MIX */ 718 SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0, 719 &wm8991_dapm_out4mix_controls[0], 720 ARRAY_SIZE(wm8991_dapm_out4mix_controls)), 721 722 /* ROPMIX */ 723 SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0, 724 &wm8991_dapm_ropmix_controls[0], 725 ARRAY_SIZE(wm8991_dapm_ropmix_controls)), 726 727 /* RONMIX */ 728 SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0, 729 &wm8991_dapm_ronmix_controls[0], 730 ARRAY_SIZE(wm8991_dapm_ronmix_controls)), 731 732 /* ROMIX */ 733 SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT, 734 0, &wm8991_dapm_romix_controls[0], 735 ARRAY_SIZE(wm8991_dapm_romix_controls), 736 outmixer_event, SND_SOC_DAPM_PRE_REG), 737 738 /* LOUT PGA */ 739 SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0, 740 NULL, 0), 741 742 /* ROUT PGA */ 743 SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0, 744 NULL, 0), 745 746 /* LOPGA */ 747 SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0, 748 NULL, 0), 749 750 /* ROPGA */ 751 SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0, 752 NULL, 0), 753 754 /* MICBIAS */ 755 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1, 756 WM8991_MICBIAS_ENA_BIT, 0, NULL, 0), 757 758 SND_SOC_DAPM_OUTPUT("LON"), 759 SND_SOC_DAPM_OUTPUT("LOP"), 760 SND_SOC_DAPM_OUTPUT("OUT3"), 761 SND_SOC_DAPM_OUTPUT("LOUT"), 762 SND_SOC_DAPM_OUTPUT("SPKN"), 763 SND_SOC_DAPM_OUTPUT("SPKP"), 764 SND_SOC_DAPM_OUTPUT("ROUT"), 765 SND_SOC_DAPM_OUTPUT("OUT4"), 766 SND_SOC_DAPM_OUTPUT("ROP"), 767 SND_SOC_DAPM_OUTPUT("RON"), 768 SND_SOC_DAPM_OUTPUT("OUT"), 769 770 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), 771}; 772 773static const struct snd_soc_dapm_route wm8991_dapm_routes[] = { 774 /* Make DACs turn on when playing even if not mixed into any outputs */ 775 {"Internal DAC Sink", NULL, "Left DAC"}, 776 {"Internal DAC Sink", NULL, "Right DAC"}, 777 778 /* Make ADCs turn on when recording even if not mixed from any inputs */ 779 {"Left ADC", NULL, "Internal ADC Source"}, 780 {"Right ADC", NULL, "Internal ADC Source"}, 781 782 /* Input Side */ 783 {"INMIXL", NULL, "INL"}, 784 {"AINLMUX", NULL, "INL"}, 785 {"INMIXR", NULL, "INR"}, 786 {"AINRMUX", NULL, "INR"}, 787 /* LIN12 PGA */ 788 {"LIN12 PGA", "LIN1 Switch", "LIN1"}, 789 {"LIN12 PGA", "LIN2 Switch", "LIN2"}, 790 /* LIN34 PGA */ 791 {"LIN34 PGA", "LIN3 Switch", "LIN3"}, 792 {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"}, 793 /* INMIXL */ 794 {"INMIXL", "Record Left Volume", "LOMIX"}, 795 {"INMIXL", "LIN2 Volume", "LIN2"}, 796 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, 797 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, 798 /* AINLMUX */ 799 {"AINLMUX", "INMIXL Mix", "INMIXL"}, 800 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, 801 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, 802 {"AINLMUX", "RXVOICE Mix", "LIN4RXN"}, 803 {"AINLMUX", "RXVOICE Mix", "RIN4RXP"}, 804 /* ADC */ 805 {"Left ADC", NULL, "AINLMUX"}, 806 807 /* RIN12 PGA */ 808 {"RIN12 PGA", "RIN1 Switch", "RIN1"}, 809 {"RIN12 PGA", "RIN2 Switch", "RIN2"}, 810 /* RIN34 PGA */ 811 {"RIN34 PGA", "RIN3 Switch", "RIN3"}, 812 {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"}, 813 /* INMIXL */ 814 {"INMIXR", "Record Right Volume", "ROMIX"}, 815 {"INMIXR", "RIN2 Volume", "RIN2"}, 816 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, 817 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, 818 /* AINRMUX */ 819 {"AINRMUX", "INMIXR Mix", "INMIXR"}, 820 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, 821 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, 822 {"AINRMUX", "RXVOICE Mix", "LIN4RXN"}, 823 {"AINRMUX", "RXVOICE Mix", "RIN4RXP"}, 824 /* ADC */ 825 {"Right ADC", NULL, "AINRMUX"}, 826 827 /* LOMIX */ 828 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, 829 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, 830 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 831 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 832 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, 833 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, 834 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, 835 836 /* ROMIX */ 837 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, 838 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, 839 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, 840 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, 841 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, 842 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, 843 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, 844 845 /* SPKMIX */ 846 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, 847 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, 848 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, 849 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, 850 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, 851 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, 852 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, 853 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, 854 855 /* LONMIX */ 856 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, 857 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, 858 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, 859 860 /* LOPMIX */ 861 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 862 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 863 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, 864 865 /* OUT3MIX */ 866 {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"}, 867 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, 868 869 /* OUT4MIX */ 870 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, 871 {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"}, 872 873 /* RONMIX */ 874 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, 875 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, 876 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, 877 878 /* ROPMIX */ 879 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, 880 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, 881 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, 882 883 /* Out Mixer PGAs */ 884 {"LOPGA", NULL, "LOMIX"}, 885 {"ROPGA", NULL, "ROMIX"}, 886 887 {"LOUT PGA", NULL, "LOMIX"}, 888 {"ROUT PGA", NULL, "ROMIX"}, 889 890 /* Output Pins */ 891 {"LON", NULL, "LONMIX"}, 892 {"LOP", NULL, "LOPMIX"}, 893 {"OUT", NULL, "OUT3MIX"}, 894 {"LOUT", NULL, "LOUT PGA"}, 895 {"SPKN", NULL, "SPKMIX"}, 896 {"ROUT", NULL, "ROUT PGA"}, 897 {"OUT4", NULL, "OUT4MIX"}, 898 {"ROP", NULL, "ROPMIX"}, 899 {"RON", NULL, "RONMIX"}, 900}; 901 902/* PLL divisors */ 903struct _pll_div { 904 u32 div2; 905 u32 n; 906 u32 k; 907}; 908 909/* The size in bits of the pll divide multiplied by 10 910 * to allow rounding later */ 911#define FIXED_PLL_SIZE ((1 << 16) * 10) 912 913static void pll_factors(struct _pll_div *pll_div, unsigned int target, 914 unsigned int source) 915{ 916 u64 Kpart; 917 unsigned int K, Ndiv, Nmod; 918 919 920 Ndiv = target / source; 921 if (Ndiv < 6) { 922 source >>= 1; 923 pll_div->div2 = 1; 924 Ndiv = target / source; 925 } else 926 pll_div->div2 = 0; 927 928 if ((Ndiv < 6) || (Ndiv > 12)) 929 printk(KERN_WARNING 930 "WM8991 N value outwith recommended range! N = %d\n", Ndiv); 931 932 pll_div->n = Ndiv; 933 Nmod = target % source; 934 Kpart = FIXED_PLL_SIZE * (long long)Nmod; 935 936 do_div(Kpart, source); 937 938 K = Kpart & 0xFFFFFFFF; 939 940 /* Check if we need to round */ 941 if ((K % 10) >= 5) 942 K += 5; 943 944 /* Move down to proper range now rounding is done */ 945 K /= 10; 946 947 pll_div->k = K; 948} 949 950static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai, 951 int pll_id, int src, unsigned int freq_in, unsigned int freq_out) 952{ 953 u16 reg; 954 struct snd_soc_codec *codec = codec_dai->codec; 955 struct _pll_div pll_div; 956 957 if (freq_in && freq_out) { 958 pll_factors(&pll_div, freq_out * 4, freq_in); 959 960 /* Turn on PLL */ 961 reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2); 962 reg |= WM8991_PLL_ENA; 963 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg); 964 965 /* sysclk comes from PLL */ 966 reg = snd_soc_read(codec, WM8991_CLOCKING_2); 967 snd_soc_write(codec, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC); 968 969 /* set up N , fractional mode and pre-divisor if necessary */ 970 snd_soc_write(codec, WM8991_PLL1, pll_div.n | WM8991_SDM | 971 (pll_div.div2 ? WM8991_PRESCALE : 0)); 972 snd_soc_write(codec, WM8991_PLL2, (u8)(pll_div.k>>8)); 973 snd_soc_write(codec, WM8991_PLL3, (u8)(pll_div.k & 0xFF)); 974 } else { 975 /* Turn on PLL */ 976 reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2); 977 reg &= ~WM8991_PLL_ENA; 978 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg); 979 } 980 return 0; 981} 982 983/* 984 * Set's ADC and Voice DAC format. 985 */ 986static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai, 987 unsigned int fmt) 988{ 989 struct snd_soc_codec *codec = codec_dai->codec; 990 u16 audio1, audio3; 991 992 audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1); 993 audio3 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_3); 994 995 /* set master/slave audio interface */ 996 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 997 case SND_SOC_DAIFMT_CBS_CFS: 998 audio3 &= ~WM8991_AIF_MSTR1; 999 break; 1000 case SND_SOC_DAIFMT_CBM_CFM: 1001 audio3 |= WM8991_AIF_MSTR1; 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 1007 audio1 &= ~WM8991_AIF_FMT_MASK; 1008 1009 /* interface format */ 1010 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1011 case SND_SOC_DAIFMT_I2S: 1012 audio1 |= WM8991_AIF_TMF_I2S; 1013 audio1 &= ~WM8991_AIF_LRCLK_INV; 1014 break; 1015 case SND_SOC_DAIFMT_RIGHT_J: 1016 audio1 |= WM8991_AIF_TMF_RIGHTJ; 1017 audio1 &= ~WM8991_AIF_LRCLK_INV; 1018 break; 1019 case SND_SOC_DAIFMT_LEFT_J: 1020 audio1 |= WM8991_AIF_TMF_LEFTJ; 1021 audio1 &= ~WM8991_AIF_LRCLK_INV; 1022 break; 1023 case SND_SOC_DAIFMT_DSP_A: 1024 audio1 |= WM8991_AIF_TMF_DSP; 1025 audio1 &= ~WM8991_AIF_LRCLK_INV; 1026 break; 1027 case SND_SOC_DAIFMT_DSP_B: 1028 audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV; 1029 break; 1030 default: 1031 return -EINVAL; 1032 } 1033 1034 snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1); 1035 snd_soc_write(codec, WM8991_AUDIO_INTERFACE_3, audio3); 1036 return 0; 1037} 1038 1039static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 1040 int div_id, int div) 1041{ 1042 struct snd_soc_codec *codec = codec_dai->codec; 1043 u16 reg; 1044 1045 switch (div_id) { 1046 case WM8991_MCLK_DIV: 1047 reg = snd_soc_read(codec, WM8991_CLOCKING_2) & 1048 ~WM8991_MCLK_DIV_MASK; 1049 snd_soc_write(codec, WM8991_CLOCKING_2, reg | div); 1050 break; 1051 case WM8991_DACCLK_DIV: 1052 reg = snd_soc_read(codec, WM8991_CLOCKING_2) & 1053 ~WM8991_DAC_CLKDIV_MASK; 1054 snd_soc_write(codec, WM8991_CLOCKING_2, reg | div); 1055 break; 1056 case WM8991_ADCCLK_DIV: 1057 reg = snd_soc_read(codec, WM8991_CLOCKING_2) & 1058 ~WM8991_ADC_CLKDIV_MASK; 1059 snd_soc_write(codec, WM8991_CLOCKING_2, reg | div); 1060 break; 1061 case WM8991_BCLK_DIV: 1062 reg = snd_soc_read(codec, WM8991_CLOCKING_1) & 1063 ~WM8991_BCLK_DIV_MASK; 1064 snd_soc_write(codec, WM8991_CLOCKING_1, reg | div); 1065 break; 1066 default: 1067 return -EINVAL; 1068 } 1069 1070 return 0; 1071} 1072 1073/* 1074 * Set PCM DAI bit size and sample rate. 1075 */ 1076static int wm8991_hw_params(struct snd_pcm_substream *substream, 1077 struct snd_pcm_hw_params *params, 1078 struct snd_soc_dai *dai) 1079{ 1080 struct snd_soc_codec *codec = dai->codec; 1081 u16 audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1); 1082 1083 audio1 &= ~WM8991_AIF_WL_MASK; 1084 /* bit size */ 1085 switch (params_width(params)) { 1086 case 16: 1087 break; 1088 case 20: 1089 audio1 |= WM8991_AIF_WL_20BITS; 1090 break; 1091 case 24: 1092 audio1 |= WM8991_AIF_WL_24BITS; 1093 break; 1094 case 32: 1095 audio1 |= WM8991_AIF_WL_32BITS; 1096 break; 1097 } 1098 1099 snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1); 1100 return 0; 1101} 1102 1103static int wm8991_mute(struct snd_soc_dai *dai, int mute) 1104{ 1105 struct snd_soc_codec *codec = dai->codec; 1106 u16 val; 1107 1108 val = snd_soc_read(codec, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE; 1109 if (mute) 1110 snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); 1111 else 1112 snd_soc_write(codec, WM8991_DAC_CTRL, val); 1113 return 0; 1114} 1115 1116static int wm8991_set_bias_level(struct snd_soc_codec *codec, 1117 enum snd_soc_bias_level level) 1118{ 1119 struct wm8991_priv *wm8991 = snd_soc_codec_get_drvdata(codec); 1120 u16 val; 1121 1122 switch (level) { 1123 case SND_SOC_BIAS_ON: 1124 break; 1125 1126 case SND_SOC_BIAS_PREPARE: 1127 /* VMID=2*50k */ 1128 val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) & 1129 ~WM8991_VMID_MODE_MASK; 1130 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x2); 1131 break; 1132 1133 case SND_SOC_BIAS_STANDBY: 1134 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1135 regcache_sync(wm8991->regmap); 1136 /* Enable all output discharge bits */ 1137 snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE | 1138 WM8991_DIS_RLINE | WM8991_DIS_OUT3 | 1139 WM8991_DIS_OUT4 | WM8991_DIS_LOUT | 1140 WM8991_DIS_ROUT); 1141 1142 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1143 snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | 1144 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1145 WM8991_VMIDTOG); 1146 1147 /* Delay to allow output caps to discharge */ 1148 msleep(300); 1149 1150 /* Disable VMIDTOG */ 1151 snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | 1152 WM8991_BUFDCOPEN | WM8991_POBCTRL); 1153 1154 /* disable all output discharge bits */ 1155 snd_soc_write(codec, WM8991_ANTIPOP1, 0); 1156 1157 /* Enable outputs */ 1158 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1b00); 1159 1160 msleep(50); 1161 1162 /* Enable VMID at 2x50k */ 1163 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f02); 1164 1165 msleep(100); 1166 1167 /* Enable VREF */ 1168 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03); 1169 1170 msleep(600); 1171 1172 /* Enable BUFIOEN */ 1173 snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | 1174 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1175 WM8991_BUFIOEN); 1176 1177 /* Disable outputs */ 1178 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x3); 1179 1180 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1181 snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_BUFIOEN); 1182 } 1183 1184 /* VMID=2*250k */ 1185 val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) & 1186 ~WM8991_VMID_MODE_MASK; 1187 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x4); 1188 break; 1189 1190 case SND_SOC_BIAS_OFF: 1191 /* Enable POBCTRL and SOFT_ST */ 1192 snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | 1193 WM8991_POBCTRL | WM8991_BUFIOEN); 1194 1195 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1196 snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | 1197 WM8991_BUFDCOPEN | WM8991_POBCTRL | 1198 WM8991_BUFIOEN); 1199 1200 /* mute DAC */ 1201 val = snd_soc_read(codec, WM8991_DAC_CTRL); 1202 snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); 1203 1204 /* Enable any disabled outputs */ 1205 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03); 1206 1207 /* Disable VMID */ 1208 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f01); 1209 1210 msleep(300); 1211 1212 /* Enable all output discharge bits */ 1213 snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE | 1214 WM8991_DIS_RLINE | WM8991_DIS_OUT3 | 1215 WM8991_DIS_OUT4 | WM8991_DIS_LOUT | 1216 WM8991_DIS_ROUT); 1217 1218 /* Disable VREF */ 1219 snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x0); 1220 1221 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1222 snd_soc_write(codec, WM8991_ANTIPOP2, 0x0); 1223 regcache_mark_dirty(wm8991->regmap); 1224 break; 1225 } 1226 1227 codec->dapm.bias_level = level; 1228 return 0; 1229} 1230 1231#define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1232 SNDRV_PCM_FMTBIT_S24_LE) 1233 1234static const struct snd_soc_dai_ops wm8991_ops = { 1235 .hw_params = wm8991_hw_params, 1236 .digital_mute = wm8991_mute, 1237 .set_fmt = wm8991_set_dai_fmt, 1238 .set_clkdiv = wm8991_set_dai_clkdiv, 1239 .set_pll = wm8991_set_dai_pll 1240}; 1241 1242/* 1243 * The WM8991 supports 2 different and mutually exclusive DAI 1244 * configurations. 1245 * 1246 * 1. ADC/DAC on Primary Interface 1247 * 2. ADC on Primary Interface/DAC on secondary 1248 */ 1249static struct snd_soc_dai_driver wm8991_dai = { 1250 /* ADC/DAC on primary */ 1251 .name = "wm8991", 1252 .id = 1, 1253 .playback = { 1254 .stream_name = "Playback", 1255 .channels_min = 1, 1256 .channels_max = 2, 1257 .rates = SNDRV_PCM_RATE_8000_96000, 1258 .formats = WM8991_FORMATS 1259 }, 1260 .capture = { 1261 .stream_name = "Capture", 1262 .channels_min = 1, 1263 .channels_max = 2, 1264 .rates = SNDRV_PCM_RATE_8000_96000, 1265 .formats = WM8991_FORMATS 1266 }, 1267 .ops = &wm8991_ops 1268}; 1269 1270static struct snd_soc_codec_driver soc_codec_dev_wm8991 = { 1271 .set_bias_level = wm8991_set_bias_level, 1272 .suspend_bias_off = true, 1273 1274 .controls = wm8991_snd_controls, 1275 .num_controls = ARRAY_SIZE(wm8991_snd_controls), 1276 .dapm_widgets = wm8991_dapm_widgets, 1277 .num_dapm_widgets = ARRAY_SIZE(wm8991_dapm_widgets), 1278 .dapm_routes = wm8991_dapm_routes, 1279 .num_dapm_routes = ARRAY_SIZE(wm8991_dapm_routes), 1280}; 1281 1282static const struct regmap_config wm8991_regmap = { 1283 .reg_bits = 8, 1284 .val_bits = 16, 1285 1286 .max_register = WM8991_PLL3, 1287 .volatile_reg = wm8991_volatile, 1288 .reg_defaults = wm8991_reg_defaults, 1289 .num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults), 1290 .cache_type = REGCACHE_RBTREE, 1291}; 1292 1293static int wm8991_i2c_probe(struct i2c_client *i2c, 1294 const struct i2c_device_id *id) 1295{ 1296 struct wm8991_priv *wm8991; 1297 unsigned int val; 1298 int ret; 1299 1300 wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL); 1301 if (!wm8991) 1302 return -ENOMEM; 1303 1304 wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap); 1305 if (IS_ERR(wm8991->regmap)) 1306 return PTR_ERR(wm8991->regmap); 1307 1308 i2c_set_clientdata(i2c, wm8991); 1309 1310 ret = regmap_read(wm8991->regmap, WM8991_RESET, &val); 1311 if (ret != 0) { 1312 dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret); 1313 return ret; 1314 } 1315 if (val != 0x8991) { 1316 dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val); 1317 return -EINVAL; 1318 } 1319 1320 ret = regmap_write(wm8991->regmap, WM8991_RESET, 0); 1321 if (ret < 0) { 1322 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 1323 return ret; 1324 } 1325 1326 regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4, 1327 WM8991_ALRCGPIO1, WM8991_ALRCGPIO1); 1328 1329 regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2, 1330 WM8991_GPIO1_SEL_MASK, 1); 1331 1332 regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1, 1333 WM8991_VREF_ENA | WM8991_VMID_MODE_MASK, 1334 WM8991_VREF_ENA | WM8991_VMID_MODE_MASK); 1335 1336 regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2, 1337 WM8991_OPCLK_ENA, WM8991_OPCLK_ENA); 1338 1339 regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0); 1340 regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME, 1341 0x50 | (1<<8)); 1342 regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME, 1343 0x50 | (1<<8)); 1344 1345 ret = snd_soc_register_codec(&i2c->dev, 1346 &soc_codec_dev_wm8991, &wm8991_dai, 1); 1347 1348 return ret; 1349} 1350 1351static int wm8991_i2c_remove(struct i2c_client *client) 1352{ 1353 snd_soc_unregister_codec(&client->dev); 1354 1355 return 0; 1356} 1357 1358static const struct i2c_device_id wm8991_i2c_id[] = { 1359 { "wm8991", 0 }, 1360 { } 1361}; 1362MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id); 1363 1364static struct i2c_driver wm8991_i2c_driver = { 1365 .driver = { 1366 .name = "wm8991", 1367 .owner = THIS_MODULE, 1368 }, 1369 .probe = wm8991_i2c_probe, 1370 .remove = wm8991_i2c_remove, 1371 .id_table = wm8991_i2c_id, 1372}; 1373 1374module_i2c_driver(wm8991_i2c_driver); 1375 1376MODULE_DESCRIPTION("ASoC WM8991 driver"); 1377MODULE_AUTHOR("Graeme Gregory"); 1378MODULE_LICENSE("GPL"); 1379