1/* 2 * wm8903.c -- WM8903 ALSA SoC Audio driver 3 * 4 * Copyright 2008-12 Wolfson Microelectronics 5 * Copyright 2011-2012 NVIDIA, Inc. 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * TODO: 14 * - TDM mode configuration. 15 * - Digital microphone support. 16 */ 17 18#include <linux/module.h> 19#include <linux/moduleparam.h> 20#include <linux/init.h> 21#include <linux/completion.h> 22#include <linux/delay.h> 23#include <linux/gpio.h> 24#include <linux/pm.h> 25#include <linux/i2c.h> 26#include <linux/regmap.h> 27#include <linux/slab.h> 28#include <linux/irq.h> 29#include <linux/mutex.h> 30#include <sound/core.h> 31#include <sound/jack.h> 32#include <sound/pcm.h> 33#include <sound/pcm_params.h> 34#include <sound/tlv.h> 35#include <sound/soc.h> 36#include <sound/initval.h> 37#include <sound/wm8903.h> 38#include <trace/events/asoc.h> 39 40#include "wm8903.h" 41 42/* Register defaults at reset */ 43static const struct reg_default wm8903_reg_defaults[] = { 44 { 4, 0x0018 }, /* R4 - Bias Control 0 */ 45 { 5, 0x0000 }, /* R5 - VMID Control 0 */ 46 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ 47 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ 48 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ 49 { 12, 0x0000 }, /* R12 - Power Management 0 */ 50 { 13, 0x0000 }, /* R13 - Power Management 1 */ 51 { 14, 0x0000 }, /* R14 - Power Management 2 */ 52 { 15, 0x0000 }, /* R15 - Power Management 3 */ 53 { 16, 0x0000 }, /* R16 - Power Management 4 */ 54 { 17, 0x0000 }, /* R17 - Power Management 5 */ 55 { 18, 0x0000 }, /* R18 - Power Management 6 */ 56 { 20, 0x0400 }, /* R20 - Clock Rates 0 */ 57 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */ 58 { 22, 0x0000 }, /* R22 - Clock Rates 2 */ 59 { 24, 0x0050 }, /* R24 - Audio Interface 0 */ 60 { 25, 0x0242 }, /* R25 - Audio Interface 1 */ 61 { 26, 0x0008 }, /* R26 - Audio Interface 2 */ 62 { 27, 0x0022 }, /* R27 - Audio Interface 3 */ 63 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ 64 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ 65 { 32, 0x0000 }, /* R32 - DAC Digital 0 */ 66 { 33, 0x0000 }, /* R33 - DAC Digital 1 */ 67 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ 68 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ 69 { 38, 0x0000 }, /* R38 - ADC Digital 0 */ 70 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */ 71 { 40, 0x09BF }, /* R40 - DRC 0 */ 72 { 41, 0x3241 }, /* R41 - DRC 1 */ 73 { 42, 0x0020 }, /* R42 - DRC 2 */ 74 { 43, 0x0000 }, /* R43 - DRC 3 */ 75 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ 76 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ 77 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ 78 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ 79 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */ 80 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */ 81 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */ 82 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */ 83 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */ 84 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */ 85 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ 86 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ 87 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ 88 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ 89 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */ 90 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */ 91 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */ 92 { 67, 0x0010 }, /* R67 - DC Servo 0 */ 93 { 69, 0x00A4 }, /* R69 - DC Servo 2 */ 94 { 90, 0x0000 }, /* R90 - Analogue HP 0 */ 95 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ 96 { 98, 0x0000 }, /* R98 - Charge Pump 0 */ 97 { 104, 0x0000 }, /* R104 - Class W 0 */ 98 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ 99 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ 100 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ 101 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ 102 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ 103 { 114, 0x0000 }, /* R114 - Control Interface */ 104 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */ 105 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */ 106 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */ 107 { 119, 0x0220 }, /* R119 - GPIO Control 4 */ 108 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */ 109 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */ 110 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */ 111 { 126, 0x0000 }, /* R126 - Interrupt Control */ 112 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */ 113 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */ 114 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */ 115 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */ 116}; 117 118struct wm8903_priv { 119 struct wm8903_platform_data *pdata; 120 struct device *dev; 121 struct regmap *regmap; 122 123 int sysclk; 124 int irq; 125 126 struct mutex lock; 127 int fs; 128 int deemph; 129 130 int dcs_pending; 131 int dcs_cache[4]; 132 133 /* Reference count */ 134 int class_w_users; 135 136 struct snd_soc_jack *mic_jack; 137 int mic_det; 138 int mic_short; 139 int mic_last_report; 140 int mic_delay; 141 142#ifdef CONFIG_GPIOLIB 143 struct gpio_chip gpio_chip; 144#endif 145}; 146 147static bool wm8903_readable_register(struct device *dev, unsigned int reg) 148{ 149 switch (reg) { 150 case WM8903_SW_RESET_AND_ID: 151 case WM8903_REVISION_NUMBER: 152 case WM8903_BIAS_CONTROL_0: 153 case WM8903_VMID_CONTROL_0: 154 case WM8903_MIC_BIAS_CONTROL_0: 155 case WM8903_ANALOGUE_DAC_0: 156 case WM8903_ANALOGUE_ADC_0: 157 case WM8903_POWER_MANAGEMENT_0: 158 case WM8903_POWER_MANAGEMENT_1: 159 case WM8903_POWER_MANAGEMENT_2: 160 case WM8903_POWER_MANAGEMENT_3: 161 case WM8903_POWER_MANAGEMENT_4: 162 case WM8903_POWER_MANAGEMENT_5: 163 case WM8903_POWER_MANAGEMENT_6: 164 case WM8903_CLOCK_RATES_0: 165 case WM8903_CLOCK_RATES_1: 166 case WM8903_CLOCK_RATES_2: 167 case WM8903_AUDIO_INTERFACE_0: 168 case WM8903_AUDIO_INTERFACE_1: 169 case WM8903_AUDIO_INTERFACE_2: 170 case WM8903_AUDIO_INTERFACE_3: 171 case WM8903_DAC_DIGITAL_VOLUME_LEFT: 172 case WM8903_DAC_DIGITAL_VOLUME_RIGHT: 173 case WM8903_DAC_DIGITAL_0: 174 case WM8903_DAC_DIGITAL_1: 175 case WM8903_ADC_DIGITAL_VOLUME_LEFT: 176 case WM8903_ADC_DIGITAL_VOLUME_RIGHT: 177 case WM8903_ADC_DIGITAL_0: 178 case WM8903_DIGITAL_MICROPHONE_0: 179 case WM8903_DRC_0: 180 case WM8903_DRC_1: 181 case WM8903_DRC_2: 182 case WM8903_DRC_3: 183 case WM8903_ANALOGUE_LEFT_INPUT_0: 184 case WM8903_ANALOGUE_RIGHT_INPUT_0: 185 case WM8903_ANALOGUE_LEFT_INPUT_1: 186 case WM8903_ANALOGUE_RIGHT_INPUT_1: 187 case WM8903_ANALOGUE_LEFT_MIX_0: 188 case WM8903_ANALOGUE_RIGHT_MIX_0: 189 case WM8903_ANALOGUE_SPK_MIX_LEFT_0: 190 case WM8903_ANALOGUE_SPK_MIX_LEFT_1: 191 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0: 192 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1: 193 case WM8903_ANALOGUE_OUT1_LEFT: 194 case WM8903_ANALOGUE_OUT1_RIGHT: 195 case WM8903_ANALOGUE_OUT2_LEFT: 196 case WM8903_ANALOGUE_OUT2_RIGHT: 197 case WM8903_ANALOGUE_OUT3_LEFT: 198 case WM8903_ANALOGUE_OUT3_RIGHT: 199 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0: 200 case WM8903_DC_SERVO_0: 201 case WM8903_DC_SERVO_2: 202 case WM8903_DC_SERVO_READBACK_1: 203 case WM8903_DC_SERVO_READBACK_2: 204 case WM8903_DC_SERVO_READBACK_3: 205 case WM8903_DC_SERVO_READBACK_4: 206 case WM8903_ANALOGUE_HP_0: 207 case WM8903_ANALOGUE_LINEOUT_0: 208 case WM8903_CHARGE_PUMP_0: 209 case WM8903_CLASS_W_0: 210 case WM8903_WRITE_SEQUENCER_0: 211 case WM8903_WRITE_SEQUENCER_1: 212 case WM8903_WRITE_SEQUENCER_2: 213 case WM8903_WRITE_SEQUENCER_3: 214 case WM8903_WRITE_SEQUENCER_4: 215 case WM8903_CONTROL_INTERFACE: 216 case WM8903_GPIO_CONTROL_1: 217 case WM8903_GPIO_CONTROL_2: 218 case WM8903_GPIO_CONTROL_3: 219 case WM8903_GPIO_CONTROL_4: 220 case WM8903_GPIO_CONTROL_5: 221 case WM8903_INTERRUPT_STATUS_1: 222 case WM8903_INTERRUPT_STATUS_1_MASK: 223 case WM8903_INTERRUPT_POLARITY_1: 224 case WM8903_INTERRUPT_CONTROL: 225 case WM8903_CLOCK_RATE_TEST_4: 226 case WM8903_ANALOGUE_OUTPUT_BIAS_0: 227 return true; 228 default: 229 return false; 230 } 231} 232 233static bool wm8903_volatile_register(struct device *dev, unsigned int reg) 234{ 235 switch (reg) { 236 case WM8903_SW_RESET_AND_ID: 237 case WM8903_REVISION_NUMBER: 238 case WM8903_INTERRUPT_STATUS_1: 239 case WM8903_WRITE_SEQUENCER_4: 240 case WM8903_DC_SERVO_READBACK_1: 241 case WM8903_DC_SERVO_READBACK_2: 242 case WM8903_DC_SERVO_READBACK_3: 243 case WM8903_DC_SERVO_READBACK_4: 244 return 1; 245 246 default: 247 return 0; 248 } 249} 250 251static int wm8903_cp_event(struct snd_soc_dapm_widget *w, 252 struct snd_kcontrol *kcontrol, int event) 253{ 254 WARN_ON(event != SND_SOC_DAPM_POST_PMU); 255 mdelay(4); 256 257 return 0; 258} 259 260static int wm8903_dcs_event(struct snd_soc_dapm_widget *w, 261 struct snd_kcontrol *kcontrol, int event) 262{ 263 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 264 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 265 266 switch (event) { 267 case SND_SOC_DAPM_POST_PMU: 268 wm8903->dcs_pending |= 1 << w->shift; 269 break; 270 case SND_SOC_DAPM_PRE_PMD: 271 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 272 1 << w->shift, 0); 273 break; 274 } 275 276 return 0; 277} 278 279#define WM8903_DCS_MODE_WRITE_STOP 0 280#define WM8903_DCS_MODE_START_STOP 2 281 282static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm, 283 enum snd_soc_dapm_type event, int subseq) 284{ 285 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm); 286 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 287 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP; 288 int i, val; 289 290 /* Complete any pending DC servo starts */ 291 if (wm8903->dcs_pending) { 292 dev_dbg(codec->dev, "Starting DC servo for %x\n", 293 wm8903->dcs_pending); 294 295 /* If we've no cached values then we need to do startup */ 296 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 297 if (!(wm8903->dcs_pending & (1 << i))) 298 continue; 299 300 if (wm8903->dcs_cache[i]) { 301 dev_dbg(codec->dev, 302 "Restore DC servo %d value %x\n", 303 3 - i, wm8903->dcs_cache[i]); 304 305 snd_soc_write(codec, WM8903_DC_SERVO_4 + i, 306 wm8903->dcs_cache[i] & 0xff); 307 } else { 308 dev_dbg(codec->dev, 309 "Calibrate DC servo %d\n", 3 - i); 310 dcs_mode = WM8903_DCS_MODE_START_STOP; 311 } 312 } 313 314 /* Don't trust the cache for analogue */ 315 if (wm8903->class_w_users) 316 dcs_mode = WM8903_DCS_MODE_START_STOP; 317 318 snd_soc_update_bits(codec, WM8903_DC_SERVO_2, 319 WM8903_DCS_MODE_MASK, dcs_mode); 320 321 snd_soc_update_bits(codec, WM8903_DC_SERVO_0, 322 WM8903_DCS_ENA_MASK, wm8903->dcs_pending); 323 324 switch (dcs_mode) { 325 case WM8903_DCS_MODE_WRITE_STOP: 326 break; 327 328 case WM8903_DCS_MODE_START_STOP: 329 msleep(270); 330 331 /* Cache the measured offsets for digital */ 332 if (wm8903->class_w_users) 333 break; 334 335 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) { 336 if (!(wm8903->dcs_pending & (1 << i))) 337 continue; 338 339 val = snd_soc_read(codec, 340 WM8903_DC_SERVO_READBACK_1 + i); 341 dev_dbg(codec->dev, "DC servo %d: %x\n", 342 3 - i, val); 343 wm8903->dcs_cache[i] = val; 344 } 345 break; 346 347 default: 348 pr_warn("DCS mode %d delay not set\n", dcs_mode); 349 break; 350 } 351 352 wm8903->dcs_pending = 0; 353 } 354} 355 356/* 357 * When used with DAC outputs only the WM8903 charge pump supports 358 * operation in class W mode, providing very low power consumption 359 * when used with digital sources. Enable and disable this mode 360 * automatically depending on the mixer configuration. 361 * 362 * All the relevant controls are simple switches. 363 */ 364static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, 365 struct snd_ctl_elem_value *ucontrol) 366{ 367 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 368 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 369 u16 reg; 370 int ret; 371 372 reg = snd_soc_read(codec, WM8903_CLASS_W_0); 373 374 /* Turn it off if we're about to enable bypass */ 375 if (ucontrol->value.integer.value[0]) { 376 if (wm8903->class_w_users == 0) { 377 dev_dbg(codec->dev, "Disabling Class W\n"); 378 snd_soc_write(codec, WM8903_CLASS_W_0, reg & 379 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 380 } 381 wm8903->class_w_users++; 382 } 383 384 /* Implement the change */ 385 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 386 387 /* If we've just disabled the last bypass path turn Class W on */ 388 if (!ucontrol->value.integer.value[0]) { 389 if (wm8903->class_w_users == 1) { 390 dev_dbg(codec->dev, "Enabling Class W\n"); 391 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 392 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 393 } 394 wm8903->class_w_users--; 395 } 396 397 dev_dbg(codec->dev, "Bypass use count now %d\n", 398 wm8903->class_w_users); 399 400 return ret; 401} 402 403#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ 404 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ 405 snd_soc_dapm_get_volsw, wm8903_class_w_put) 406 407 408static int wm8903_deemph[] = { 0, 32000, 44100, 48000 }; 409 410static int wm8903_set_deemph(struct snd_soc_codec *codec) 411{ 412 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 413 int val, i, best; 414 415 /* If we're using deemphasis select the nearest available sample 416 * rate. 417 */ 418 if (wm8903->deemph) { 419 best = 1; 420 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) { 421 if (abs(wm8903_deemph[i] - wm8903->fs) < 422 abs(wm8903_deemph[best] - wm8903->fs)) 423 best = i; 424 } 425 426 val = best << WM8903_DEEMPH_SHIFT; 427 } else { 428 best = 0; 429 val = 0; 430 } 431 432 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n", 433 best, wm8903_deemph[best]); 434 435 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1, 436 WM8903_DEEMPH_MASK, val); 437} 438 439static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 440 struct snd_ctl_elem_value *ucontrol) 441{ 442 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 443 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 444 445 ucontrol->value.integer.value[0] = wm8903->deemph; 446 447 return 0; 448} 449 450static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 451 struct snd_ctl_elem_value *ucontrol) 452{ 453 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 454 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 455 int deemph = ucontrol->value.integer.value[0]; 456 int ret = 0; 457 458 if (deemph > 1) 459 return -EINVAL; 460 461 mutex_lock(&wm8903->lock); 462 if (wm8903->deemph != deemph) { 463 wm8903->deemph = deemph; 464 465 wm8903_set_deemph(codec); 466 467 ret = 1; 468 } 469 mutex_unlock(&wm8903->lock); 470 471 return ret; 472} 473 474/* ALSA can only do steps of .01dB */ 475static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 476 477static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); 478 479static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); 480static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 481 482static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 483static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); 484static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); 485static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 486static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 487 488static const char *hpf_mode_text[] = { 489 "Hi-fi", "Voice 1", "Voice 2", "Voice 3" 490}; 491 492static SOC_ENUM_SINGLE_DECL(hpf_mode, 493 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text); 494 495static const char *osr_text[] = { 496 "Low power", "High performance" 497}; 498 499static SOC_ENUM_SINGLE_DECL(adc_osr, 500 WM8903_ANALOGUE_ADC_0, 0, osr_text); 501 502static SOC_ENUM_SINGLE_DECL(dac_osr, 503 WM8903_DAC_DIGITAL_1, 0, osr_text); 504 505static const char *drc_slope_text[] = { 506 "1", "1/2", "1/4", "1/8", "1/16", "0" 507}; 508 509static SOC_ENUM_SINGLE_DECL(drc_slope_r0, 510 WM8903_DRC_2, 3, drc_slope_text); 511 512static SOC_ENUM_SINGLE_DECL(drc_slope_r1, 513 WM8903_DRC_2, 0, drc_slope_text); 514 515static const char *drc_attack_text[] = { 516 "instantaneous", 517 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", 518 "46.4ms", "92.8ms", "185.6ms" 519}; 520 521static SOC_ENUM_SINGLE_DECL(drc_attack, 522 WM8903_DRC_1, 12, drc_attack_text); 523 524static const char *drc_decay_text[] = { 525 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", 526 "23.87s", "47.56s" 527}; 528 529static SOC_ENUM_SINGLE_DECL(drc_decay, 530 WM8903_DRC_1, 8, drc_decay_text); 531 532static const char *drc_ff_delay_text[] = { 533 "5 samples", "9 samples" 534}; 535 536static SOC_ENUM_SINGLE_DECL(drc_ff_delay, 537 WM8903_DRC_0, 5, drc_ff_delay_text); 538 539static const char *drc_qr_decay_text[] = { 540 "0.725ms", "1.45ms", "5.8ms" 541}; 542 543static SOC_ENUM_SINGLE_DECL(drc_qr_decay, 544 WM8903_DRC_1, 4, drc_qr_decay_text); 545 546static const char *drc_smoothing_text[] = { 547 "Low", "Medium", "High" 548}; 549 550static SOC_ENUM_SINGLE_DECL(drc_smoothing, 551 WM8903_DRC_0, 11, drc_smoothing_text); 552 553static const char *soft_mute_text[] = { 554 "Fast (fs/2)", "Slow (fs/32)" 555}; 556 557static SOC_ENUM_SINGLE_DECL(soft_mute, 558 WM8903_DAC_DIGITAL_1, 10, soft_mute_text); 559 560static const char *mute_mode_text[] = { 561 "Hard", "Soft" 562}; 563 564static SOC_ENUM_SINGLE_DECL(mute_mode, 565 WM8903_DAC_DIGITAL_1, 9, mute_mode_text); 566 567static const char *companding_text[] = { 568 "ulaw", "alaw" 569}; 570 571static SOC_ENUM_SINGLE_DECL(dac_companding, 572 WM8903_AUDIO_INTERFACE_0, 0, companding_text); 573 574static SOC_ENUM_SINGLE_DECL(adc_companding, 575 WM8903_AUDIO_INTERFACE_0, 2, companding_text); 576 577static const char *input_mode_text[] = { 578 "Single-Ended", "Differential Line", "Differential Mic" 579}; 580 581static SOC_ENUM_SINGLE_DECL(linput_mode_enum, 582 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text); 583 584static SOC_ENUM_SINGLE_DECL(rinput_mode_enum, 585 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text); 586 587static const char *linput_mux_text[] = { 588 "IN1L", "IN2L", "IN3L" 589}; 590 591static SOC_ENUM_SINGLE_DECL(linput_enum, 592 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text); 593 594static SOC_ENUM_SINGLE_DECL(linput_inv_enum, 595 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text); 596 597static const char *rinput_mux_text[] = { 598 "IN1R", "IN2R", "IN3R" 599}; 600 601static SOC_ENUM_SINGLE_DECL(rinput_enum, 602 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text); 603 604static SOC_ENUM_SINGLE_DECL(rinput_inv_enum, 605 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text); 606 607 608static const char *sidetone_text[] = { 609 "None", "Left", "Right" 610}; 611 612static SOC_ENUM_SINGLE_DECL(lsidetone_enum, 613 WM8903_DAC_DIGITAL_0, 2, sidetone_text); 614 615static SOC_ENUM_SINGLE_DECL(rsidetone_enum, 616 WM8903_DAC_DIGITAL_0, 0, sidetone_text); 617 618static const char *adcinput_text[] = { 619 "ADC", "DMIC" 620}; 621 622static SOC_ENUM_SINGLE_DECL(adcinput_enum, 623 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text); 624 625static const char *aif_text[] = { 626 "Left", "Right" 627}; 628 629static SOC_ENUM_SINGLE_DECL(lcapture_enum, 630 WM8903_AUDIO_INTERFACE_0, 7, aif_text); 631 632static SOC_ENUM_SINGLE_DECL(rcapture_enum, 633 WM8903_AUDIO_INTERFACE_0, 6, aif_text); 634 635static SOC_ENUM_SINGLE_DECL(lplay_enum, 636 WM8903_AUDIO_INTERFACE_0, 5, aif_text); 637 638static SOC_ENUM_SINGLE_DECL(rplay_enum, 639 WM8903_AUDIO_INTERFACE_0, 4, aif_text); 640 641static const struct snd_kcontrol_new wm8903_snd_controls[] = { 642 643/* Input PGAs - No TLV since the scale depends on PGA mode */ 644SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, 645 7, 1, 1), 646SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, 647 0, 31, 0), 648SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, 649 6, 1, 0), 650 651SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, 652 7, 1, 1), 653SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, 654 0, 31, 0), 655SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, 656 6, 1, 0), 657 658/* ADCs */ 659SOC_ENUM("ADC OSR", adc_osr), 660SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0), 661SOC_ENUM("HPF Mode", hpf_mode), 662SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 663SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 664SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 665SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, 666 drc_tlv_thresh), 667SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), 668SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), 669SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), 670SOC_ENUM("DRC Attack Rate", drc_attack), 671SOC_ENUM("DRC Decay Rate", drc_decay), 672SOC_ENUM("DRC FF Delay", drc_ff_delay), 673SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), 674SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), 675SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), 676SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), 677SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), 678SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), 679SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), 680SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), 681 682SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, 683 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 684SOC_ENUM("ADC Companding Mode", adc_companding), 685SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 686 687SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, 688 12, 0, digital_sidetone_tlv), 689 690/* DAC */ 691SOC_ENUM("DAC OSR", dac_osr), 692SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 693 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 694SOC_ENUM("DAC Soft Mute Rate", soft_mute), 695SOC_ENUM("DAC Mute Mode", mute_mode), 696SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 697SOC_ENUM("DAC Companding Mode", dac_companding), 698SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 699SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0, 700 dac_boost_tlv), 701SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0, 702 wm8903_get_deemph, wm8903_put_deemph), 703 704/* Headphones */ 705SOC_DOUBLE_R("Headphone Switch", 706 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 707 8, 1, 1), 708SOC_DOUBLE_R("Headphone ZC Switch", 709 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 710 6, 1, 0), 711SOC_DOUBLE_R_TLV("Headphone Volume", 712 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, 713 0, 63, 0, out_tlv), 714 715/* Line out */ 716SOC_DOUBLE_R("Line Out Switch", 717 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 718 8, 1, 1), 719SOC_DOUBLE_R("Line Out ZC Switch", 720 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 721 6, 1, 0), 722SOC_DOUBLE_R_TLV("Line Out Volume", 723 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, 724 0, 63, 0, out_tlv), 725 726/* Speaker */ 727SOC_DOUBLE_R("Speaker Switch", 728 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), 729SOC_DOUBLE_R("Speaker ZC Switch", 730 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), 731SOC_DOUBLE_R_TLV("Speaker Volume", 732 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 733 0, 63, 0, out_tlv), 734}; 735 736static const struct snd_kcontrol_new linput_mode_mux = 737 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); 738 739static const struct snd_kcontrol_new rinput_mode_mux = 740 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); 741 742static const struct snd_kcontrol_new linput_mux = 743 SOC_DAPM_ENUM("Left Input Mux", linput_enum); 744 745static const struct snd_kcontrol_new linput_inv_mux = 746 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); 747 748static const struct snd_kcontrol_new rinput_mux = 749 SOC_DAPM_ENUM("Right Input Mux", rinput_enum); 750 751static const struct snd_kcontrol_new rinput_inv_mux = 752 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 753 754static const struct snd_kcontrol_new lsidetone_mux = 755 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); 756 757static const struct snd_kcontrol_new rsidetone_mux = 758 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); 759 760static const struct snd_kcontrol_new adcinput_mux = 761 SOC_DAPM_ENUM("ADC Input", adcinput_enum); 762 763static const struct snd_kcontrol_new lcapture_mux = 764 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum); 765 766static const struct snd_kcontrol_new rcapture_mux = 767 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum); 768 769static const struct snd_kcontrol_new lplay_mux = 770 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum); 771 772static const struct snd_kcontrol_new rplay_mux = 773 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum); 774 775static const struct snd_kcontrol_new left_output_mixer[] = { 776SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 777SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 778SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), 779SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), 780}; 781 782static const struct snd_kcontrol_new right_output_mixer[] = { 783SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), 784SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), 785SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), 786SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), 787}; 788 789static const struct snd_kcontrol_new left_speaker_mixer[] = { 790SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), 791SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), 792SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), 793SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 794 0, 1, 0), 795}; 796 797static const struct snd_kcontrol_new right_speaker_mixer[] = { 798SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), 799SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), 800SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 801 1, 1, 0), 802SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 803 0, 1, 0), 804}; 805 806static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { 807SND_SOC_DAPM_INPUT("IN1L"), 808SND_SOC_DAPM_INPUT("IN1R"), 809SND_SOC_DAPM_INPUT("IN2L"), 810SND_SOC_DAPM_INPUT("IN2R"), 811SND_SOC_DAPM_INPUT("IN3L"), 812SND_SOC_DAPM_INPUT("IN3R"), 813SND_SOC_DAPM_INPUT("DMICDAT"), 814 815SND_SOC_DAPM_OUTPUT("HPOUTL"), 816SND_SOC_DAPM_OUTPUT("HPOUTR"), 817SND_SOC_DAPM_OUTPUT("LINEOUTL"), 818SND_SOC_DAPM_OUTPUT("LINEOUTR"), 819SND_SOC_DAPM_OUTPUT("LOP"), 820SND_SOC_DAPM_OUTPUT("LON"), 821SND_SOC_DAPM_OUTPUT("ROP"), 822SND_SOC_DAPM_OUTPUT("RON"), 823 824SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), 825 826SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), 827SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, 828 &linput_inv_mux), 829SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), 830 831SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), 832SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, 833 &rinput_inv_mux), 834SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), 835 836SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), 837SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), 838 839SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 840SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux), 841 842SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0), 843SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0), 844 845SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux), 846SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux), 847 848SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 849SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 850 851SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), 852SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), 853 854SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0), 855SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0), 856 857SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux), 858SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux), 859 860SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0), 861SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0), 862 863SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, 864 left_output_mixer, ARRAY_SIZE(left_output_mixer)), 865SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, 866 right_output_mixer, ARRAY_SIZE(right_output_mixer)), 867 868SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, 869 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 870SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, 871 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 872 873SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 874 1, 0, NULL, 0), 875SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2, 876 0, 0, NULL, 0), 877 878SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0, 879 NULL, 0), 880SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0, 881 NULL, 0), 882 883SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0), 884SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0), 885SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0), 886SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0), 887SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0), 888SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0), 889SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0), 890SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0), 891 892SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0, 893 NULL, 0), 894SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0, 895 NULL, 0), 896SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0, 897 NULL, 0), 898SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0, 899 NULL, 0), 900SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0, 901 NULL, 0), 902SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0, 903 NULL, 0), 904SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0, 905 NULL, 0), 906SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0, 907 NULL, 0), 908 909SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0), 910SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event, 911 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 912SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event, 913 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 914SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event, 915 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 916SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event, 917 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 918 919SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 920 NULL, 0), 921SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 922 NULL, 0), 923 924SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, 925 wm8903_cp_event, SND_SOC_DAPM_POST_PMU), 926SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), 927SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0), 928}; 929 930static const struct snd_soc_dapm_route wm8903_intercon[] = { 931 932 { "CLK_DSP", NULL, "CLK_SYS" }, 933 { "MICBIAS", NULL, "CLK_SYS" }, 934 { "HPL_DCS", NULL, "CLK_SYS" }, 935 { "HPR_DCS", NULL, "CLK_SYS" }, 936 { "LINEOUTL_DCS", NULL, "CLK_SYS" }, 937 { "LINEOUTR_DCS", NULL, "CLK_SYS" }, 938 939 { "Left Input Mux", "IN1L", "IN1L" }, 940 { "Left Input Mux", "IN2L", "IN2L" }, 941 { "Left Input Mux", "IN3L", "IN3L" }, 942 943 { "Left Input Inverting Mux", "IN1L", "IN1L" }, 944 { "Left Input Inverting Mux", "IN2L", "IN2L" }, 945 { "Left Input Inverting Mux", "IN3L", "IN3L" }, 946 947 { "Right Input Mux", "IN1R", "IN1R" }, 948 { "Right Input Mux", "IN2R", "IN2R" }, 949 { "Right Input Mux", "IN3R", "IN3R" }, 950 951 { "Right Input Inverting Mux", "IN1R", "IN1R" }, 952 { "Right Input Inverting Mux", "IN2R", "IN2R" }, 953 { "Right Input Inverting Mux", "IN3R", "IN3R" }, 954 955 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, 956 { "Left Input Mode Mux", "Differential Line", 957 "Left Input Mux" }, 958 { "Left Input Mode Mux", "Differential Line", 959 "Left Input Inverting Mux" }, 960 { "Left Input Mode Mux", "Differential Mic", 961 "Left Input Mux" }, 962 { "Left Input Mode Mux", "Differential Mic", 963 "Left Input Inverting Mux" }, 964 965 { "Right Input Mode Mux", "Single-Ended", 966 "Right Input Inverting Mux" }, 967 { "Right Input Mode Mux", "Differential Line", 968 "Right Input Mux" }, 969 { "Right Input Mode Mux", "Differential Line", 970 "Right Input Inverting Mux" }, 971 { "Right Input Mode Mux", "Differential Mic", 972 "Right Input Mux" }, 973 { "Right Input Mode Mux", "Differential Mic", 974 "Right Input Inverting Mux" }, 975 976 { "Left Input PGA", NULL, "Left Input Mode Mux" }, 977 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 978 979 { "Left ADC Input", "ADC", "Left Input PGA" }, 980 { "Left ADC Input", "DMIC", "DMICDAT" }, 981 { "Right ADC Input", "ADC", "Right Input PGA" }, 982 { "Right ADC Input", "DMIC", "DMICDAT" }, 983 984 { "Left Capture Mux", "Left", "ADCL" }, 985 { "Left Capture Mux", "Right", "ADCR" }, 986 987 { "Right Capture Mux", "Left", "ADCL" }, 988 { "Right Capture Mux", "Right", "ADCR" }, 989 990 { "AIFTXL", NULL, "Left Capture Mux" }, 991 { "AIFTXR", NULL, "Right Capture Mux" }, 992 993 { "ADCL", NULL, "Left ADC Input" }, 994 { "ADCL", NULL, "CLK_DSP" }, 995 { "ADCR", NULL, "Right ADC Input" }, 996 { "ADCR", NULL, "CLK_DSP" }, 997 998 { "Left Playback Mux", "Left", "AIFRXL" }, 999 { "Left Playback Mux", "Right", "AIFRXR" }, 1000 1001 { "Right Playback Mux", "Left", "AIFRXL" }, 1002 { "Right Playback Mux", "Right", "AIFRXR" }, 1003 1004 { "DACL Sidetone", "Left", "ADCL" }, 1005 { "DACL Sidetone", "Right", "ADCR" }, 1006 { "DACR Sidetone", "Left", "ADCL" }, 1007 { "DACR Sidetone", "Right", "ADCR" }, 1008 1009 { "DACL", NULL, "Left Playback Mux" }, 1010 { "DACL", NULL, "DACL Sidetone" }, 1011 { "DACL", NULL, "CLK_DSP" }, 1012 1013 { "DACR", NULL, "Right Playback Mux" }, 1014 { "DACR", NULL, "DACR Sidetone" }, 1015 { "DACR", NULL, "CLK_DSP" }, 1016 1017 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1018 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1019 { "Left Output Mixer", "DACL Switch", "DACL" }, 1020 { "Left Output Mixer", "DACR Switch", "DACR" }, 1021 1022 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 1023 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 1024 { "Right Output Mixer", "DACL Switch", "DACL" }, 1025 { "Right Output Mixer", "DACR Switch", "DACR" }, 1026 1027 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1028 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1029 { "Left Speaker Mixer", "DACL Switch", "DACL" }, 1030 { "Left Speaker Mixer", "DACR Switch", "DACR" }, 1031 1032 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, 1033 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, 1034 { "Right Speaker Mixer", "DACL Switch", "DACL" }, 1035 { "Right Speaker Mixer", "DACR Switch", "DACR" }, 1036 1037 { "Left Line Output PGA", NULL, "Left Output Mixer" }, 1038 { "Right Line Output PGA", NULL, "Right Output Mixer" }, 1039 1040 { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, 1041 { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, 1042 1043 { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, 1044 { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, 1045 1046 { "HPL_ENA", NULL, "Left Headphone Output PGA" }, 1047 { "HPR_ENA", NULL, "Right Headphone Output PGA" }, 1048 { "HPL_ENA_DLY", NULL, "HPL_ENA" }, 1049 { "HPR_ENA_DLY", NULL, "HPR_ENA" }, 1050 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" }, 1051 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" }, 1052 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" }, 1053 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" }, 1054 1055 { "HPL_DCS", NULL, "DCS Master" }, 1056 { "HPR_DCS", NULL, "DCS Master" }, 1057 { "LINEOUTL_DCS", NULL, "DCS Master" }, 1058 { "LINEOUTR_DCS", NULL, "DCS Master" }, 1059 1060 { "HPL_DCS", NULL, "HPL_ENA_DLY" }, 1061 { "HPR_DCS", NULL, "HPR_ENA_DLY" }, 1062 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" }, 1063 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" }, 1064 1065 { "HPL_ENA_OUTP", NULL, "HPL_DCS" }, 1066 { "HPR_ENA_OUTP", NULL, "HPR_DCS" }, 1067 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" }, 1068 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" }, 1069 1070 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" }, 1071 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" }, 1072 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" }, 1073 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" }, 1074 1075 { "HPOUTL", NULL, "HPL_RMV_SHORT" }, 1076 { "HPOUTR", NULL, "HPR_RMV_SHORT" }, 1077 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" }, 1078 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" }, 1079 1080 { "LOP", NULL, "Left Speaker PGA" }, 1081 { "LON", NULL, "Left Speaker PGA" }, 1082 1083 { "ROP", NULL, "Right Speaker PGA" }, 1084 { "RON", NULL, "Right Speaker PGA" }, 1085 1086 { "Charge Pump", NULL, "CLK_DSP" }, 1087 1088 { "Left Headphone Output PGA", NULL, "Charge Pump" }, 1089 { "Right Headphone Output PGA", NULL, "Charge Pump" }, 1090 { "Left Line Output PGA", NULL, "Charge Pump" }, 1091 { "Right Line Output PGA", NULL, "Charge Pump" }, 1092}; 1093 1094static int wm8903_set_bias_level(struct snd_soc_codec *codec, 1095 enum snd_soc_bias_level level) 1096{ 1097 switch (level) { 1098 case SND_SOC_BIAS_ON: 1099 break; 1100 1101 case SND_SOC_BIAS_PREPARE: 1102 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1103 WM8903_VMID_RES_MASK, 1104 WM8903_VMID_RES_50K); 1105 break; 1106 1107 case SND_SOC_BIAS_STANDBY: 1108 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1109 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1110 WM8903_POBCTRL | WM8903_ISEL_MASK | 1111 WM8903_STARTUP_BIAS_ENA | 1112 WM8903_BIAS_ENA, 1113 WM8903_POBCTRL | 1114 (2 << WM8903_ISEL_SHIFT) | 1115 WM8903_STARTUP_BIAS_ENA); 1116 1117 snd_soc_update_bits(codec, 1118 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1119 WM8903_SPK_DISCHARGE, 1120 WM8903_SPK_DISCHARGE); 1121 1122 msleep(33); 1123 1124 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1125 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1126 WM8903_SPKL_ENA | WM8903_SPKR_ENA); 1127 1128 snd_soc_update_bits(codec, 1129 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0, 1130 WM8903_SPK_DISCHARGE, 0); 1131 1132 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1133 WM8903_VMID_TIE_ENA | 1134 WM8903_BUFIO_ENA | 1135 WM8903_VMID_IO_ENA | 1136 WM8903_VMID_SOFT_MASK | 1137 WM8903_VMID_RES_MASK | 1138 WM8903_VMID_BUF_ENA, 1139 WM8903_VMID_TIE_ENA | 1140 WM8903_BUFIO_ENA | 1141 WM8903_VMID_IO_ENA | 1142 (2 << WM8903_VMID_SOFT_SHIFT) | 1143 WM8903_VMID_RES_250K | 1144 WM8903_VMID_BUF_ENA); 1145 1146 msleep(129); 1147 1148 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5, 1149 WM8903_SPKL_ENA | WM8903_SPKR_ENA, 1150 0); 1151 1152 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1153 WM8903_VMID_SOFT_MASK, 0); 1154 1155 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1156 WM8903_VMID_RES_MASK, 1157 WM8903_VMID_RES_50K); 1158 1159 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1160 WM8903_BIAS_ENA | WM8903_POBCTRL, 1161 WM8903_BIAS_ENA); 1162 1163 /* By default no bypass paths are enabled so 1164 * enable Class W support. 1165 */ 1166 dev_dbg(codec->dev, "Enabling Class W\n"); 1167 snd_soc_update_bits(codec, WM8903_CLASS_W_0, 1168 WM8903_CP_DYN_FREQ | 1169 WM8903_CP_DYN_V, 1170 WM8903_CP_DYN_FREQ | 1171 WM8903_CP_DYN_V); 1172 } 1173 1174 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1175 WM8903_VMID_RES_MASK, 1176 WM8903_VMID_RES_250K); 1177 break; 1178 1179 case SND_SOC_BIAS_OFF: 1180 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1181 WM8903_BIAS_ENA, 0); 1182 1183 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1184 WM8903_VMID_SOFT_MASK, 1185 2 << WM8903_VMID_SOFT_SHIFT); 1186 1187 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1188 WM8903_VMID_BUF_ENA, 0); 1189 1190 msleep(290); 1191 1192 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0, 1193 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA | 1194 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK | 1195 WM8903_VMID_SOFT_MASK | 1196 WM8903_VMID_BUF_ENA, 0); 1197 1198 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0, 1199 WM8903_STARTUP_BIAS_ENA, 0); 1200 break; 1201 } 1202 1203 codec->dapm.bias_level = level; 1204 1205 return 0; 1206} 1207 1208static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1209 int clk_id, unsigned int freq, int dir) 1210{ 1211 struct snd_soc_codec *codec = codec_dai->codec; 1212 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1213 1214 wm8903->sysclk = freq; 1215 1216 return 0; 1217} 1218 1219static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, 1220 unsigned int fmt) 1221{ 1222 struct snd_soc_codec *codec = codec_dai->codec; 1223 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1224 1225 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1226 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1227 1228 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1229 case SND_SOC_DAIFMT_CBS_CFS: 1230 break; 1231 case SND_SOC_DAIFMT_CBS_CFM: 1232 aif1 |= WM8903_LRCLK_DIR; 1233 break; 1234 case SND_SOC_DAIFMT_CBM_CFM: 1235 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; 1236 break; 1237 case SND_SOC_DAIFMT_CBM_CFS: 1238 aif1 |= WM8903_BCLK_DIR; 1239 break; 1240 default: 1241 return -EINVAL; 1242 } 1243 1244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1245 case SND_SOC_DAIFMT_DSP_A: 1246 aif1 |= 0x3; 1247 break; 1248 case SND_SOC_DAIFMT_DSP_B: 1249 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; 1250 break; 1251 case SND_SOC_DAIFMT_I2S: 1252 aif1 |= 0x2; 1253 break; 1254 case SND_SOC_DAIFMT_RIGHT_J: 1255 aif1 |= 0x1; 1256 break; 1257 case SND_SOC_DAIFMT_LEFT_J: 1258 break; 1259 default: 1260 return -EINVAL; 1261 } 1262 1263 /* Clock inversion */ 1264 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1265 case SND_SOC_DAIFMT_DSP_A: 1266 case SND_SOC_DAIFMT_DSP_B: 1267 /* frame inversion not valid for DSP modes */ 1268 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1269 case SND_SOC_DAIFMT_NB_NF: 1270 break; 1271 case SND_SOC_DAIFMT_IB_NF: 1272 aif1 |= WM8903_AIF_BCLK_INV; 1273 break; 1274 default: 1275 return -EINVAL; 1276 } 1277 break; 1278 case SND_SOC_DAIFMT_I2S: 1279 case SND_SOC_DAIFMT_RIGHT_J: 1280 case SND_SOC_DAIFMT_LEFT_J: 1281 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1282 case SND_SOC_DAIFMT_NB_NF: 1283 break; 1284 case SND_SOC_DAIFMT_IB_IF: 1285 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; 1286 break; 1287 case SND_SOC_DAIFMT_IB_NF: 1288 aif1 |= WM8903_AIF_BCLK_INV; 1289 break; 1290 case SND_SOC_DAIFMT_NB_IF: 1291 aif1 |= WM8903_AIF_LRCLK_INV; 1292 break; 1293 default: 1294 return -EINVAL; 1295 } 1296 break; 1297 default: 1298 return -EINVAL; 1299 } 1300 1301 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1302 1303 return 0; 1304} 1305 1306static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1307{ 1308 struct snd_soc_codec *codec = codec_dai->codec; 1309 u16 reg; 1310 1311 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1312 1313 if (mute) 1314 reg |= WM8903_DAC_MUTE; 1315 else 1316 reg &= ~WM8903_DAC_MUTE; 1317 1318 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); 1319 1320 return 0; 1321} 1322 1323/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended 1324 * for optimal performance so we list the lower rates first and match 1325 * on the last match we find. */ 1326static struct { 1327 int div; 1328 int rate; 1329 int mode; 1330 int mclk_div; 1331} clk_sys_ratios[] = { 1332 { 64, 0x0, 0x0, 1 }, 1333 { 68, 0x0, 0x1, 1 }, 1334 { 125, 0x0, 0x2, 1 }, 1335 { 128, 0x1, 0x0, 1 }, 1336 { 136, 0x1, 0x1, 1 }, 1337 { 192, 0x2, 0x0, 1 }, 1338 { 204, 0x2, 0x1, 1 }, 1339 1340 { 64, 0x0, 0x0, 2 }, 1341 { 68, 0x0, 0x1, 2 }, 1342 { 125, 0x0, 0x2, 2 }, 1343 { 128, 0x1, 0x0, 2 }, 1344 { 136, 0x1, 0x1, 2 }, 1345 { 192, 0x2, 0x0, 2 }, 1346 { 204, 0x2, 0x1, 2 }, 1347 1348 { 250, 0x2, 0x2, 1 }, 1349 { 256, 0x3, 0x0, 1 }, 1350 { 272, 0x3, 0x1, 1 }, 1351 { 384, 0x4, 0x0, 1 }, 1352 { 408, 0x4, 0x1, 1 }, 1353 { 375, 0x4, 0x2, 1 }, 1354 { 512, 0x5, 0x0, 1 }, 1355 { 544, 0x5, 0x1, 1 }, 1356 { 500, 0x5, 0x2, 1 }, 1357 { 768, 0x6, 0x0, 1 }, 1358 { 816, 0x6, 0x1, 1 }, 1359 { 750, 0x6, 0x2, 1 }, 1360 { 1024, 0x7, 0x0, 1 }, 1361 { 1088, 0x7, 0x1, 1 }, 1362 { 1000, 0x7, 0x2, 1 }, 1363 { 1408, 0x8, 0x0, 1 }, 1364 { 1496, 0x8, 0x1, 1 }, 1365 { 1536, 0x9, 0x0, 1 }, 1366 { 1632, 0x9, 0x1, 1 }, 1367 { 1500, 0x9, 0x2, 1 }, 1368 1369 { 250, 0x2, 0x2, 2 }, 1370 { 256, 0x3, 0x0, 2 }, 1371 { 272, 0x3, 0x1, 2 }, 1372 { 384, 0x4, 0x0, 2 }, 1373 { 408, 0x4, 0x1, 2 }, 1374 { 375, 0x4, 0x2, 2 }, 1375 { 512, 0x5, 0x0, 2 }, 1376 { 544, 0x5, 0x1, 2 }, 1377 { 500, 0x5, 0x2, 2 }, 1378 { 768, 0x6, 0x0, 2 }, 1379 { 816, 0x6, 0x1, 2 }, 1380 { 750, 0x6, 0x2, 2 }, 1381 { 1024, 0x7, 0x0, 2 }, 1382 { 1088, 0x7, 0x1, 2 }, 1383 { 1000, 0x7, 0x2, 2 }, 1384 { 1408, 0x8, 0x0, 2 }, 1385 { 1496, 0x8, 0x1, 2 }, 1386 { 1536, 0x9, 0x0, 2 }, 1387 { 1632, 0x9, 0x1, 2 }, 1388 { 1500, 0x9, 0x2, 2 }, 1389}; 1390 1391/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1392static struct { 1393 int ratio; 1394 int div; 1395} bclk_divs[] = { 1396 { 10, 0 }, 1397 { 20, 2 }, 1398 { 30, 3 }, 1399 { 40, 4 }, 1400 { 50, 5 }, 1401 { 60, 7 }, 1402 { 80, 8 }, 1403 { 100, 9 }, 1404 { 120, 11 }, 1405 { 160, 12 }, 1406 { 200, 13 }, 1407 { 220, 14 }, 1408 { 240, 15 }, 1409 { 300, 17 }, 1410 { 320, 18 }, 1411 { 440, 19 }, 1412 { 480, 20 }, 1413}; 1414 1415/* Sample rates for DSP */ 1416static struct { 1417 int rate; 1418 int value; 1419} sample_rates[] = { 1420 { 8000, 0 }, 1421 { 11025, 1 }, 1422 { 12000, 2 }, 1423 { 16000, 3 }, 1424 { 22050, 4 }, 1425 { 24000, 5 }, 1426 { 32000, 6 }, 1427 { 44100, 7 }, 1428 { 48000, 8 }, 1429 { 88200, 9 }, 1430 { 96000, 10 }, 1431 { 0, 0 }, 1432}; 1433 1434static int wm8903_hw_params(struct snd_pcm_substream *substream, 1435 struct snd_pcm_hw_params *params, 1436 struct snd_soc_dai *dai) 1437{ 1438 struct snd_soc_codec *codec = dai->codec; 1439 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1440 int fs = params_rate(params); 1441 int bclk; 1442 int bclk_div; 1443 int i; 1444 int dsp_config; 1445 int clk_config; 1446 int best_val; 1447 int cur_val; 1448 int clk_sys; 1449 1450 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); 1451 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); 1452 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); 1453 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); 1454 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1455 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1456 1457 /* Enable sloping stopband filter for low sample rates */ 1458 if (fs <= 24000) 1459 dac_digital1 |= WM8903_DAC_SB_FILT; 1460 else 1461 dac_digital1 &= ~WM8903_DAC_SB_FILT; 1462 1463 /* Configure sample rate logic for DSP - choose nearest rate */ 1464 dsp_config = 0; 1465 best_val = abs(sample_rates[dsp_config].rate - fs); 1466 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { 1467 cur_val = abs(sample_rates[i].rate - fs); 1468 if (cur_val <= best_val) { 1469 dsp_config = i; 1470 best_val = cur_val; 1471 } 1472 } 1473 1474 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1475 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1476 clock1 |= sample_rates[dsp_config].value; 1477 1478 aif1 &= ~WM8903_AIF_WL_MASK; 1479 bclk = 2 * fs; 1480 switch (params_width(params)) { 1481 case 16: 1482 bclk *= 16; 1483 break; 1484 case 20: 1485 bclk *= 20; 1486 aif1 |= 0x4; 1487 break; 1488 case 24: 1489 bclk *= 24; 1490 aif1 |= 0x8; 1491 break; 1492 case 32: 1493 bclk *= 32; 1494 aif1 |= 0xc; 1495 break; 1496 default: 1497 return -EINVAL; 1498 } 1499 1500 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", 1501 wm8903->sysclk, fs); 1502 1503 /* We may not have an MCLK which allows us to generate exactly 1504 * the clock we want, particularly with USB derived inputs, so 1505 * approximate. 1506 */ 1507 clk_config = 0; 1508 best_val = abs((wm8903->sysclk / 1509 (clk_sys_ratios[0].mclk_div * 1510 clk_sys_ratios[0].div)) - fs); 1511 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { 1512 cur_val = abs((wm8903->sysclk / 1513 (clk_sys_ratios[i].mclk_div * 1514 clk_sys_ratios[i].div)) - fs); 1515 1516 if (cur_val <= best_val) { 1517 clk_config = i; 1518 best_val = cur_val; 1519 } 1520 } 1521 1522 if (clk_sys_ratios[clk_config].mclk_div == 2) { 1523 clock0 |= WM8903_MCLKDIV2; 1524 clk_sys = wm8903->sysclk / 2; 1525 } else { 1526 clock0 &= ~WM8903_MCLKDIV2; 1527 clk_sys = wm8903->sysclk; 1528 } 1529 1530 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | 1531 WM8903_CLK_SYS_MODE_MASK); 1532 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; 1533 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; 1534 1535 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", 1536 clk_sys_ratios[clk_config].rate, 1537 clk_sys_ratios[clk_config].mode, 1538 clk_sys_ratios[clk_config].div); 1539 1540 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); 1541 1542 /* We may not get quite the right frequency if using 1543 * approximate clocks so look for the closest match that is 1544 * higher than the target (we need to ensure that there enough 1545 * BCLKs to clock out the samples). 1546 */ 1547 bclk_div = 0; 1548 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; 1549 i = 1; 1550 while (i < ARRAY_SIZE(bclk_divs)) { 1551 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; 1552 if (cur_val < 0) /* BCLK table is sorted */ 1553 break; 1554 bclk_div = i; 1555 best_val = cur_val; 1556 i++; 1557 } 1558 1559 aif2 &= ~WM8903_BCLK_DIV_MASK; 1560 aif3 &= ~WM8903_LRCLK_RATE_MASK; 1561 1562 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", 1563 bclk_divs[bclk_div].ratio / 10, bclk, 1564 (clk_sys * 10) / bclk_divs[bclk_div].ratio); 1565 1566 aif2 |= bclk_divs[bclk_div].div; 1567 aif3 |= bclk / fs; 1568 1569 wm8903->fs = params_rate(params); 1570 wm8903_set_deemph(codec); 1571 1572 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1573 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1574 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1575 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1576 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1577 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1578 1579 return 0; 1580} 1581 1582/** 1583 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ 1584 * 1585 * @codec: WM8903 codec 1586 * @jack: jack to report detection events on 1587 * @det: value to report for presence detection 1588 * @shrt: value to report for short detection 1589 * 1590 * Enable microphone detection via IRQ on the WM8903. If GPIOs are 1591 * being used to bring out signals to the processor then only platform 1592 * data configuration is needed for WM8903 and processor GPIOs should 1593 * be configured using snd_soc_jack_add_gpios() instead. 1594 * 1595 * The current threasholds for detection should be configured using 1596 * micdet_cfg in the platform data. Using this function will force on 1597 * the microphone bias for the device. 1598 */ 1599int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 1600 int det, int shrt) 1601{ 1602 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1603 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; 1604 1605 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", 1606 det, shrt); 1607 1608 /* Store the configuration */ 1609 wm8903->mic_jack = jack; 1610 wm8903->mic_det = det; 1611 wm8903->mic_short = shrt; 1612 1613 /* Enable interrupts we've got a report configured for */ 1614 if (det) 1615 irq_mask &= ~WM8903_MICDET_EINT; 1616 if (shrt) 1617 irq_mask &= ~WM8903_MICSHRT_EINT; 1618 1619 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, 1620 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, 1621 irq_mask); 1622 1623 if (det || shrt) { 1624 /* Enable mic detection, this may not have been set through 1625 * platform data (eg, if the defaults are OK). */ 1626 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, 1627 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 1628 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1629 WM8903_MICDET_ENA, WM8903_MICDET_ENA); 1630 } else { 1631 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, 1632 WM8903_MICDET_ENA, 0); 1633 } 1634 1635 return 0; 1636} 1637EXPORT_SYMBOL_GPL(wm8903_mic_detect); 1638 1639static irqreturn_t wm8903_irq(int irq, void *data) 1640{ 1641 struct wm8903_priv *wm8903 = data; 1642 int mic_report, ret; 1643 unsigned int int_val, mask, int_pol; 1644 1645 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK, 1646 &mask); 1647 if (ret != 0) { 1648 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret); 1649 return IRQ_NONE; 1650 } 1651 1652 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val); 1653 if (ret != 0) { 1654 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret); 1655 return IRQ_NONE; 1656 } 1657 1658 int_val &= ~mask; 1659 1660 if (int_val & WM8903_WSEQ_BUSY_EINT) { 1661 dev_warn(wm8903->dev, "Write sequencer done\n"); 1662 } 1663 1664 /* 1665 * The rest is microphone jack detection. We need to manually 1666 * invert the polarity of the interrupt after each event - to 1667 * simplify the code keep track of the last state we reported 1668 * and just invert the relevant bits in both the report and 1669 * the polarity register. 1670 */ 1671 mic_report = wm8903->mic_last_report; 1672 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1673 &int_pol); 1674 if (ret != 0) { 1675 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n", 1676 ret); 1677 return IRQ_HANDLED; 1678 } 1679 1680#ifndef CONFIG_SND_SOC_WM8903_MODULE 1681 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT)) 1682 trace_snd_soc_jack_irq(dev_name(wm8903->dev)); 1683#endif 1684 1685 if (int_val & WM8903_MICSHRT_EINT) { 1686 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol); 1687 1688 mic_report ^= wm8903->mic_short; 1689 int_pol ^= WM8903_MICSHRT_INV; 1690 } 1691 1692 if (int_val & WM8903_MICDET_EINT) { 1693 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol); 1694 1695 mic_report ^= wm8903->mic_det; 1696 int_pol ^= WM8903_MICDET_INV; 1697 1698 msleep(wm8903->mic_delay); 1699 } 1700 1701 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1, 1702 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); 1703 1704 snd_soc_jack_report(wm8903->mic_jack, mic_report, 1705 wm8903->mic_short | wm8903->mic_det); 1706 1707 wm8903->mic_last_report = mic_report; 1708 1709 return IRQ_HANDLED; 1710} 1711 1712#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ 1713 SNDRV_PCM_RATE_11025 | \ 1714 SNDRV_PCM_RATE_16000 | \ 1715 SNDRV_PCM_RATE_22050 | \ 1716 SNDRV_PCM_RATE_32000 | \ 1717 SNDRV_PCM_RATE_44100 | \ 1718 SNDRV_PCM_RATE_48000 | \ 1719 SNDRV_PCM_RATE_88200 | \ 1720 SNDRV_PCM_RATE_96000) 1721 1722#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1723 SNDRV_PCM_RATE_11025 | \ 1724 SNDRV_PCM_RATE_16000 | \ 1725 SNDRV_PCM_RATE_22050 | \ 1726 SNDRV_PCM_RATE_32000 | \ 1727 SNDRV_PCM_RATE_44100 | \ 1728 SNDRV_PCM_RATE_48000) 1729 1730#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1731 SNDRV_PCM_FMTBIT_S20_3LE |\ 1732 SNDRV_PCM_FMTBIT_S24_LE) 1733 1734static const struct snd_soc_dai_ops wm8903_dai_ops = { 1735 .hw_params = wm8903_hw_params, 1736 .digital_mute = wm8903_digital_mute, 1737 .set_fmt = wm8903_set_dai_fmt, 1738 .set_sysclk = wm8903_set_dai_sysclk, 1739}; 1740 1741static struct snd_soc_dai_driver wm8903_dai = { 1742 .name = "wm8903-hifi", 1743 .playback = { 1744 .stream_name = "Playback", 1745 .channels_min = 2, 1746 .channels_max = 2, 1747 .rates = WM8903_PLAYBACK_RATES, 1748 .formats = WM8903_FORMATS, 1749 }, 1750 .capture = { 1751 .stream_name = "Capture", 1752 .channels_min = 2, 1753 .channels_max = 2, 1754 .rates = WM8903_CAPTURE_RATES, 1755 .formats = WM8903_FORMATS, 1756 }, 1757 .ops = &wm8903_dai_ops, 1758 .symmetric_rates = 1, 1759}; 1760 1761static int wm8903_resume(struct snd_soc_codec *codec) 1762{ 1763 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1764 1765 regcache_sync(wm8903->regmap); 1766 1767 return 0; 1768} 1769 1770#ifdef CONFIG_GPIOLIB 1771static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip) 1772{ 1773 return container_of(chip, struct wm8903_priv, gpio_chip); 1774} 1775 1776static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset) 1777{ 1778 if (offset >= WM8903_NUM_GPIO) 1779 return -EINVAL; 1780 1781 return 0; 1782} 1783 1784static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 1785{ 1786 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1787 unsigned int mask, val; 1788 int ret; 1789 1790 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; 1791 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) | 1792 WM8903_GP1_DIR; 1793 1794 ret = regmap_update_bits(wm8903->regmap, 1795 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1796 if (ret < 0) 1797 return ret; 1798 1799 return 0; 1800} 1801 1802static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset) 1803{ 1804 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1805 unsigned int reg; 1806 1807 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®); 1808 1809 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT; 1810} 1811 1812static int wm8903_gpio_direction_out(struct gpio_chip *chip, 1813 unsigned offset, int value) 1814{ 1815 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1816 unsigned int mask, val; 1817 int ret; 1818 1819 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; 1820 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) | 1821 (value << WM8903_GP2_LVL_SHIFT); 1822 1823 ret = regmap_update_bits(wm8903->regmap, 1824 WM8903_GPIO_CONTROL_1 + offset, mask, val); 1825 if (ret < 0) 1826 return ret; 1827 1828 return 0; 1829} 1830 1831static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1832{ 1833 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip); 1834 1835 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, 1836 WM8903_GP1_LVL_MASK, 1837 !!value << WM8903_GP1_LVL_SHIFT); 1838} 1839 1840static struct gpio_chip wm8903_template_chip = { 1841 .label = "wm8903", 1842 .owner = THIS_MODULE, 1843 .request = wm8903_gpio_request, 1844 .direction_input = wm8903_gpio_direction_in, 1845 .get = wm8903_gpio_get, 1846 .direction_output = wm8903_gpio_direction_out, 1847 .set = wm8903_gpio_set, 1848 .can_sleep = 1, 1849}; 1850 1851static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1852{ 1853 struct wm8903_platform_data *pdata = wm8903->pdata; 1854 int ret; 1855 1856 wm8903->gpio_chip = wm8903_template_chip; 1857 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO; 1858 wm8903->gpio_chip.dev = wm8903->dev; 1859 1860 if (pdata->gpio_base) 1861 wm8903->gpio_chip.base = pdata->gpio_base; 1862 else 1863 wm8903->gpio_chip.base = -1; 1864 1865 ret = gpiochip_add(&wm8903->gpio_chip); 1866 if (ret != 0) 1867 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret); 1868} 1869 1870static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1871{ 1872 gpiochip_remove(&wm8903->gpio_chip); 1873} 1874#else 1875static void wm8903_init_gpio(struct wm8903_priv *wm8903) 1876{ 1877} 1878 1879static void wm8903_free_gpio(struct wm8903_priv *wm8903) 1880{ 1881} 1882#endif 1883 1884static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { 1885 .resume = wm8903_resume, 1886 .set_bias_level = wm8903_set_bias_level, 1887 .seq_notifier = wm8903_seq_notifier, 1888 .suspend_bias_off = true, 1889 1890 .controls = wm8903_snd_controls, 1891 .num_controls = ARRAY_SIZE(wm8903_snd_controls), 1892 .dapm_widgets = wm8903_dapm_widgets, 1893 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets), 1894 .dapm_routes = wm8903_intercon, 1895 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon), 1896}; 1897 1898static const struct regmap_config wm8903_regmap = { 1899 .reg_bits = 8, 1900 .val_bits = 16, 1901 1902 .max_register = WM8903_MAX_REGISTER, 1903 .volatile_reg = wm8903_volatile_register, 1904 .readable_reg = wm8903_readable_register, 1905 1906 .cache_type = REGCACHE_RBTREE, 1907 .reg_defaults = wm8903_reg_defaults, 1908 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults), 1909}; 1910 1911static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c, 1912 struct wm8903_platform_data *pdata) 1913{ 1914 struct irq_data *irq_data = irq_get_irq_data(i2c->irq); 1915 if (!irq_data) { 1916 dev_err(&i2c->dev, "Invalid IRQ: %d\n", 1917 i2c->irq); 1918 return -EINVAL; 1919 } 1920 1921 switch (irqd_get_trigger_type(irq_data)) { 1922 case IRQ_TYPE_NONE: 1923 default: 1924 /* 1925 * We assume the controller imposes no restrictions, 1926 * so we are able to select active-high 1927 */ 1928 /* Fall-through */ 1929 case IRQ_TYPE_LEVEL_HIGH: 1930 pdata->irq_active_low = false; 1931 break; 1932 case IRQ_TYPE_LEVEL_LOW: 1933 pdata->irq_active_low = true; 1934 break; 1935 } 1936 1937 return 0; 1938} 1939 1940static int wm8903_set_pdata_from_of(struct i2c_client *i2c, 1941 struct wm8903_platform_data *pdata) 1942{ 1943 const struct device_node *np = i2c->dev.of_node; 1944 u32 val32; 1945 int i; 1946 1947 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0) 1948 pdata->micdet_cfg = val32; 1949 1950 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0) 1951 pdata->micdet_delay = val32; 1952 1953 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg, 1954 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) { 1955 /* 1956 * In device tree: 0 means "write 0", 1957 * 0xffffffff means "don't touch". 1958 * 1959 * In platform data: 0 means "don't touch", 1960 * 0x8000 means "write 0". 1961 * 1962 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000. 1963 * 1964 * Convert from DT to pdata representation here, 1965 * so no other code needs to change. 1966 */ 1967 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 1968 if (pdata->gpio_cfg[i] == 0) { 1969 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO; 1970 } else if (pdata->gpio_cfg[i] == 0xffffffff) { 1971 pdata->gpio_cfg[i] = 0; 1972 } else if (pdata->gpio_cfg[i] > 0x7fff) { 1973 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n", 1974 i, pdata->gpio_cfg[i]); 1975 return -EINVAL; 1976 } 1977 } 1978 } 1979 1980 return 0; 1981} 1982 1983static int wm8903_i2c_probe(struct i2c_client *i2c, 1984 const struct i2c_device_id *id) 1985{ 1986 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev); 1987 struct wm8903_priv *wm8903; 1988 int trigger; 1989 bool mic_gpio = false; 1990 unsigned int val, irq_pol; 1991 int ret, i; 1992 1993 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv), 1994 GFP_KERNEL); 1995 if (wm8903 == NULL) 1996 return -ENOMEM; 1997 1998 mutex_init(&wm8903->lock); 1999 wm8903->dev = &i2c->dev; 2000 2001 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap); 2002 if (IS_ERR(wm8903->regmap)) { 2003 ret = PTR_ERR(wm8903->regmap); 2004 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2005 ret); 2006 return ret; 2007 } 2008 2009 i2c_set_clientdata(i2c, wm8903); 2010 2011 /* If no platform data was supplied, create storage for defaults */ 2012 if (pdata) { 2013 wm8903->pdata = pdata; 2014 } else { 2015 wm8903->pdata = devm_kzalloc(&i2c->dev, 2016 sizeof(struct wm8903_platform_data), 2017 GFP_KERNEL); 2018 if (wm8903->pdata == NULL) { 2019 dev_err(&i2c->dev, "Failed to allocate pdata\n"); 2020 return -ENOMEM; 2021 } 2022 2023 if (i2c->irq) { 2024 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata); 2025 if (ret != 0) 2026 return ret; 2027 } 2028 2029 if (i2c->dev.of_node) { 2030 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata); 2031 if (ret != 0) 2032 return ret; 2033 } 2034 } 2035 2036 pdata = wm8903->pdata; 2037 2038 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val); 2039 if (ret != 0) { 2040 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); 2041 goto err; 2042 } 2043 if (val != 0x8903) { 2044 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val); 2045 ret = -ENODEV; 2046 goto err; 2047 } 2048 2049 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val); 2050 if (ret != 0) { 2051 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret); 2052 goto err; 2053 } 2054 dev_info(&i2c->dev, "WM8903 revision %c\n", 2055 (val & WM8903_CHIP_REV_MASK) + 'A'); 2056 2057 /* Reset the device */ 2058 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903); 2059 2060 wm8903_init_gpio(wm8903); 2061 2062 /* Set up GPIO pin state, detect if any are MIC detect outputs */ 2063 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { 2064 if ((!pdata->gpio_cfg[i]) || 2065 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO)) 2066 continue; 2067 2068 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i, 2069 pdata->gpio_cfg[i] & 0x7fff); 2070 2071 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK) 2072 >> WM8903_GP1_FN_SHIFT; 2073 2074 switch (val) { 2075 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT: 2076 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT: 2077 mic_gpio = true; 2078 break; 2079 default: 2080 break; 2081 } 2082 } 2083 2084 /* Set up microphone detection */ 2085 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0, 2086 pdata->micdet_cfg); 2087 2088 /* Microphone detection needs the WSEQ clock */ 2089 if (pdata->micdet_cfg) 2090 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0, 2091 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); 2092 2093 /* If microphone detection is enabled by pdata but 2094 * detected via IRQ then interrupts can be lost before 2095 * the machine driver has set up microphone detection 2096 * IRQs as the IRQs are clear on read. The detection 2097 * will be enabled when the machine driver configures. 2098 */ 2099 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA)); 2100 2101 wm8903->mic_delay = pdata->micdet_delay; 2102 2103 if (i2c->irq) { 2104 if (pdata->irq_active_low) { 2105 trigger = IRQF_TRIGGER_LOW; 2106 irq_pol = WM8903_IRQ_POL; 2107 } else { 2108 trigger = IRQF_TRIGGER_HIGH; 2109 irq_pol = 0; 2110 } 2111 2112 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL, 2113 WM8903_IRQ_POL, irq_pol); 2114 2115 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq, 2116 trigger | IRQF_ONESHOT, 2117 "wm8903", wm8903); 2118 if (ret != 0) { 2119 dev_err(wm8903->dev, "Failed to request IRQ: %d\n", 2120 ret); 2121 return ret; 2122 } 2123 2124 /* Enable write sequencer interrupts */ 2125 regmap_update_bits(wm8903->regmap, 2126 WM8903_INTERRUPT_STATUS_1_MASK, 2127 WM8903_IM_WSEQ_BUSY_EINT, 0); 2128 } 2129 2130 /* Latch volume update bits */ 2131 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT, 2132 WM8903_ADCVU, WM8903_ADCVU); 2133 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT, 2134 WM8903_ADCVU, WM8903_ADCVU); 2135 2136 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT, 2137 WM8903_DACVU, WM8903_DACVU); 2138 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT, 2139 WM8903_DACVU, WM8903_DACVU); 2140 2141 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT, 2142 WM8903_HPOUTVU, WM8903_HPOUTVU); 2143 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT, 2144 WM8903_HPOUTVU, WM8903_HPOUTVU); 2145 2146 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT, 2147 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2148 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT, 2149 WM8903_LINEOUTVU, WM8903_LINEOUTVU); 2150 2151 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT, 2152 WM8903_SPKVU, WM8903_SPKVU); 2153 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT, 2154 WM8903_SPKVU, WM8903_SPKVU); 2155 2156 /* Enable DAC soft mute by default */ 2157 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1, 2158 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE, 2159 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE); 2160 2161 ret = snd_soc_register_codec(&i2c->dev, 2162 &soc_codec_dev_wm8903, &wm8903_dai, 1); 2163 if (ret != 0) 2164 goto err; 2165 2166 return 0; 2167err: 2168 return ret; 2169} 2170 2171static int wm8903_i2c_remove(struct i2c_client *client) 2172{ 2173 struct wm8903_priv *wm8903 = i2c_get_clientdata(client); 2174 2175 if (client->irq) 2176 free_irq(client->irq, wm8903); 2177 wm8903_free_gpio(wm8903); 2178 snd_soc_unregister_codec(&client->dev); 2179 2180 return 0; 2181} 2182 2183static const struct of_device_id wm8903_of_match[] = { 2184 { .compatible = "wlf,wm8903", }, 2185 {}, 2186}; 2187MODULE_DEVICE_TABLE(of, wm8903_of_match); 2188 2189static const struct i2c_device_id wm8903_i2c_id[] = { 2190 { "wm8903", 0 }, 2191 { } 2192}; 2193MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); 2194 2195static struct i2c_driver wm8903_i2c_driver = { 2196 .driver = { 2197 .name = "wm8903", 2198 .owner = THIS_MODULE, 2199 .of_match_table = wm8903_of_match, 2200 }, 2201 .probe = wm8903_i2c_probe, 2202 .remove = wm8903_i2c_remove, 2203 .id_table = wm8903_i2c_id, 2204}; 2205 2206module_i2c_driver(wm8903_i2c_driver); 2207 2208MODULE_DESCRIPTION("ASoC WM8903 driver"); 2209MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); 2210MODULE_LICENSE("GPL"); 2211