1#ifndef __ADAU1373_H__
2#define __ADAU1373_H__
3
4enum adau1373_pll_src {
5	ADAU1373_PLL_SRC_MCLK1 = 0,
6	ADAU1373_PLL_SRC_BCLK1 = 1,
7	ADAU1373_PLL_SRC_BCLK2 = 2,
8	ADAU1373_PLL_SRC_BCLK3 = 3,
9	ADAU1373_PLL_SRC_LRCLK1 = 4,
10	ADAU1373_PLL_SRC_LRCLK2 = 5,
11	ADAU1373_PLL_SRC_LRCLK3 = 6,
12	ADAU1373_PLL_SRC_GPIO1 = 7,
13	ADAU1373_PLL_SRC_GPIO2 = 8,
14	ADAU1373_PLL_SRC_GPIO3 = 9,
15	ADAU1373_PLL_SRC_GPIO4 = 10,
16	ADAU1373_PLL_SRC_MCLK2 = 11,
17};
18
19enum adau1373_pll {
20	ADAU1373_PLL1 = 0,
21	ADAU1373_PLL2 = 1,
22};
23
24enum adau1373_clk_src {
25	ADAU1373_CLK_SRC_PLL1 = 0,
26	ADAU1373_CLK_SRC_PLL2 = 1,
27};
28
29#endif
30