1/*
2 * include/linux/spi/spidev.h
3 *
4 * Copyright (C) 2006 SWAPP
5 *	Andrea Paterniani <a.paterniani@swapp-eng.it>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21
22#ifndef SPIDEV_H
23#define SPIDEV_H
24
25#include <linux/types.h>
26
27/* User space versions of kernel symbols for SPI clocking modes,
28 * matching <linux/spi/spi.h>
29 */
30
31#define SPI_CPHA		0x01
32#define SPI_CPOL		0x02
33
34#define SPI_MODE_0		(0|0)
35#define SPI_MODE_1		(0|SPI_CPHA)
36#define SPI_MODE_2		(SPI_CPOL|0)
37#define SPI_MODE_3		(SPI_CPOL|SPI_CPHA)
38
39#define SPI_CS_HIGH		0x04
40#define SPI_LSB_FIRST		0x08
41#define SPI_3WIRE		0x10
42#define SPI_LOOP		0x20
43#define SPI_NO_CS		0x40
44#define SPI_READY		0x80
45#define SPI_TX_DUAL		0x100
46#define SPI_TX_QUAD		0x200
47#define SPI_RX_DUAL		0x400
48#define SPI_RX_QUAD		0x800
49
50/*---------------------------------------------------------------------------*/
51
52/* IOCTL commands */
53
54#define SPI_IOC_MAGIC			'k'
55
56/**
57 * struct spi_ioc_transfer - describes a single SPI transfer
58 * @tx_buf: Holds pointer to userspace buffer with transmit data, or null.
59 *	If no data is provided, zeroes are shifted out.
60 * @rx_buf: Holds pointer to userspace buffer for receive data, or null.
61 * @len: Length of tx and rx buffers, in bytes.
62 * @speed_hz: Temporary override of the device's bitrate.
63 * @bits_per_word: Temporary override of the device's wordsize.
64 * @delay_usecs: If nonzero, how long to delay after the last bit transfer
65 *	before optionally deselecting the device before the next transfer.
66 * @cs_change: True to deselect device before starting the next transfer.
67 *
68 * This structure is mapped directly to the kernel spi_transfer structure;
69 * the fields have the same meanings, except of course that the pointers
70 * are in a different address space (and may be of different sizes in some
71 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
72 * Zero-initialize the structure, including currently unused fields, to
73 * accommodate potential future updates.
74 *
75 * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync().
76 * Pass it an array of related transfers, they'll execute together.
77 * Each transfer may be half duplex (either direction) or full duplex.
78 *
79 *	struct spi_ioc_transfer mesg[4];
80 *	...
81 *	status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg);
82 *
83 * So for example one transfer might send a nine bit command (right aligned
84 * in a 16-bit word), the next could read a block of 8-bit data before
85 * terminating that command by temporarily deselecting the chip; the next
86 * could send a different nine bit command (re-selecting the chip), and the
87 * last transfer might write some register values.
88 */
89struct spi_ioc_transfer {
90	__u64		tx_buf;
91	__u64		rx_buf;
92
93	__u32		len;
94	__u32		speed_hz;
95
96	__u16		delay_usecs;
97	__u8		bits_per_word;
98	__u8		cs_change;
99	__u8		tx_nbits;
100	__u8		rx_nbits;
101	__u16		pad;
102
103	/* If the contents of 'struct spi_ioc_transfer' ever change
104	 * incompatibly, then the ioctl number (currently 0) must change;
105	 * ioctls with constant size fields get a bit more in the way of
106	 * error checking than ones (like this) where that field varies.
107	 *
108	 * NOTE: struct layout is the same in 64bit and 32bit userspace.
109	 */
110};
111
112/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
113#define SPI_MSGSIZE(N) \
114	((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
115		? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
116#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
117
118
119/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) (limited to 8 bits) */
120#define SPI_IOC_RD_MODE			_IOR(SPI_IOC_MAGIC, 1, __u8)
121#define SPI_IOC_WR_MODE			_IOW(SPI_IOC_MAGIC, 1, __u8)
122
123/* Read / Write SPI bit justification */
124#define SPI_IOC_RD_LSB_FIRST		_IOR(SPI_IOC_MAGIC, 2, __u8)
125#define SPI_IOC_WR_LSB_FIRST		_IOW(SPI_IOC_MAGIC, 2, __u8)
126
127/* Read / Write SPI device word length (1..N) */
128#define SPI_IOC_RD_BITS_PER_WORD	_IOR(SPI_IOC_MAGIC, 3, __u8)
129#define SPI_IOC_WR_BITS_PER_WORD	_IOW(SPI_IOC_MAGIC, 3, __u8)
130
131/* Read / Write SPI device default max speed hz */
132#define SPI_IOC_RD_MAX_SPEED_HZ		_IOR(SPI_IOC_MAGIC, 4, __u32)
133#define SPI_IOC_WR_MAX_SPEED_HZ		_IOW(SPI_IOC_MAGIC, 4, __u32)
134
135/* Read / Write of the SPI mode field */
136#define SPI_IOC_RD_MODE32		_IOR(SPI_IOC_MAGIC, 5, __u32)
137#define SPI_IOC_WR_MODE32		_IOW(SPI_IOC_MAGIC, 5, __u32)
138
139
140
141#endif /* SPIDEV_H */
142