1/* 2 * Copyright (c) 2014 Linaro Ltd. 3 * Copyright (c) 2014 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10#ifndef __DTS_HIX5HD2_CLOCK_H 11#define __DTS_HIX5HD2_CLOCK_H 12 13/* fixed rate */ 14#define HIX5HD2_FIXED_1200M 1 15#define HIX5HD2_FIXED_400M 2 16#define HIX5HD2_FIXED_48M 3 17#define HIX5HD2_FIXED_24M 4 18#define HIX5HD2_FIXED_600M 5 19#define HIX5HD2_FIXED_300M 6 20#define HIX5HD2_FIXED_75M 7 21#define HIX5HD2_FIXED_200M 8 22#define HIX5HD2_FIXED_100M 9 23#define HIX5HD2_FIXED_40M 10 24#define HIX5HD2_FIXED_150M 11 25#define HIX5HD2_FIXED_1728M 12 26#define HIX5HD2_FIXED_28P8M 13 27#define HIX5HD2_FIXED_432M 14 28#define HIX5HD2_FIXED_345P6M 15 29#define HIX5HD2_FIXED_288M 16 30#define HIX5HD2_FIXED_60M 17 31#define HIX5HD2_FIXED_750M 18 32#define HIX5HD2_FIXED_500M 19 33#define HIX5HD2_FIXED_54M 20 34#define HIX5HD2_FIXED_27M 21 35#define HIX5HD2_FIXED_1500M 22 36#define HIX5HD2_FIXED_375M 23 37#define HIX5HD2_FIXED_187M 24 38#define HIX5HD2_FIXED_250M 25 39#define HIX5HD2_FIXED_125M 26 40#define HIX5HD2_FIXED_2P02M 27 41#define HIX5HD2_FIXED_50M 28 42#define HIX5HD2_FIXED_25M 29 43#define HIX5HD2_FIXED_83M 30 44 45/* mux clocks */ 46#define HIX5HD2_SFC_MUX 64 47#define HIX5HD2_MMC_MUX 65 48#define HIX5HD2_FEPHY_MUX 66 49#define HIX5HD2_SD_MUX 67 50 51/* gate clocks */ 52#define HIX5HD2_SFC_RST 128 53#define HIX5HD2_SFC_CLK 129 54#define HIX5HD2_MMC_CIU_CLK 130 55#define HIX5HD2_MMC_BIU_CLK 131 56#define HIX5HD2_MMC_CIU_RST 132 57#define HIX5HD2_FWD_BUS_CLK 133 58#define HIX5HD2_FWD_SYS_CLK 134 59#define HIX5HD2_MAC0_PHY_CLK 135 60#define HIX5HD2_SD_CIU_CLK 136 61#define HIX5HD2_SD_BIU_CLK 137 62#define HIX5HD2_SD_CIU_RST 138 63#define HIX5HD2_WDG0_CLK 139 64#define HIX5HD2_WDG0_RST 140 65#define HIX5HD2_I2C0_CLK 141 66#define HIX5HD2_I2C0_RST 142 67#define HIX5HD2_I2C1_CLK 143 68#define HIX5HD2_I2C1_RST 144 69#define HIX5HD2_I2C2_CLK 145 70#define HIX5HD2_I2C2_RST 146 71#define HIX5HD2_I2C3_CLK 147 72#define HIX5HD2_I2C3_RST 148 73#define HIX5HD2_I2C4_CLK 149 74#define HIX5HD2_I2C4_RST 150 75#define HIX5HD2_I2C5_CLK 151 76#define HIX5HD2_I2C5_RST 152 77 78/* complex */ 79#define HIX5HD2_MAC0_CLK 192 80#define HIX5HD2_MAC1_CLK 193 81#define HIX5HD2_SATA_CLK 194 82#define HIX5HD2_USB_CLK 195 83 84#define HIX5HD2_NR_CLKS 256 85#endif /* __DTS_HIX5HD2_CLOCK_H */ 86