1/* 2 * Copyright (C) 2010 Juergen Beisert, Pengutronix 3 * 4 * This code is based on: 5 * Author: Vitaly Wool <vital@embeddedalley.com> 6 * 7 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20#define DRIVER_NAME "mxsfb" 21 22/** 23 * @file 24 * @brief LCDIF driver for i.MX23 and i.MX28 25 * 26 * The LCDIF support four modes of operation 27 * - MPU interface (to drive smart displays) -> not supported yet 28 * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet 29 * - Dotclock interface (to drive LC displays with RGB data and sync signals) 30 * - DVI (to drive ITU-R BT656) -> not supported yet 31 * 32 * This driver depends on a correct setup of the pins used for this purpose 33 * (platform specific). 34 * 35 * For the developer: Don't forget to set the data bus width to the display 36 * in the imx_fb_videomode structure. You will else end up with ugly colours. 37 * If you fight against jitter you can vary the clock delay. This is a feature 38 * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give 39 * the required value in the imx_fb_videomode structure. 40 */ 41 42#include <linux/module.h> 43#include <linux/kernel.h> 44#include <linux/of_device.h> 45#include <linux/platform_device.h> 46#include <linux/clk.h> 47#include <linux/dma-mapping.h> 48#include <linux/io.h> 49#include <linux/fb.h> 50#include <linux/regulator/consumer.h> 51#include <video/of_display_timing.h> 52#include <video/of_videomode.h> 53#include <video/videomode.h> 54 55#define REG_SET 4 56#define REG_CLR 8 57 58#define LCDC_CTRL 0x00 59#define LCDC_CTRL1 0x10 60#define LCDC_V4_CTRL2 0x20 61#define LCDC_V3_TRANSFER_COUNT 0x20 62#define LCDC_V4_TRANSFER_COUNT 0x30 63#define LCDC_V4_CUR_BUF 0x40 64#define LCDC_V4_NEXT_BUF 0x50 65#define LCDC_V3_CUR_BUF 0x30 66#define LCDC_V3_NEXT_BUF 0x40 67#define LCDC_TIMING 0x60 68#define LCDC_VDCTRL0 0x70 69#define LCDC_VDCTRL1 0x80 70#define LCDC_VDCTRL2 0x90 71#define LCDC_VDCTRL3 0xa0 72#define LCDC_VDCTRL4 0xb0 73#define LCDC_DVICTRL0 0xc0 74#define LCDC_DVICTRL1 0xd0 75#define LCDC_DVICTRL2 0xe0 76#define LCDC_DVICTRL3 0xf0 77#define LCDC_DVICTRL4 0x100 78#define LCDC_V4_DATA 0x180 79#define LCDC_V3_DATA 0x1b0 80#define LCDC_V4_DEBUG0 0x1d0 81#define LCDC_V3_DEBUG0 0x1f0 82 83#define CTRL_SFTRST (1 << 31) 84#define CTRL_CLKGATE (1 << 30) 85#define CTRL_BYPASS_COUNT (1 << 19) 86#define CTRL_VSYNC_MODE (1 << 18) 87#define CTRL_DOTCLK_MODE (1 << 17) 88#define CTRL_DATA_SELECT (1 << 16) 89#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) 90#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) 91#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) 92#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) 93#define CTRL_MASTER (1 << 5) 94#define CTRL_DF16 (1 << 3) 95#define CTRL_DF18 (1 << 2) 96#define CTRL_DF24 (1 << 1) 97#define CTRL_RUN (1 << 0) 98 99#define CTRL1_FIFO_CLEAR (1 << 21) 100#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) 101#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) 102 103#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) 104#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) 105#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) 106#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) 107 108 109#define VDCTRL0_ENABLE_PRESENT (1 << 28) 110#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) 111#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) 112#define VDCTRL0_DOTCLK_ACT_FALLING (1 << 25) 113#define VDCTRL0_ENABLE_ACT_HIGH (1 << 24) 114#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) 115#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) 116#define VDCTRL0_HALF_LINE (1 << 19) 117#define VDCTRL0_HALF_LINE_MODE (1 << 18) 118#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) 119#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) 120 121#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) 122#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) 123 124#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) 125#define VDCTRL3_VSYNC_ONLY (1 << 28) 126#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) 127#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) 128#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) 129#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) 130 131#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ 132#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ 133#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) 134#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) 135 136#define DEBUG0_HSYNC (1 < 26) 137#define DEBUG0_VSYNC (1 < 25) 138 139#define MIN_XRES 120 140#define MIN_YRES 120 141 142#define RED 0 143#define GREEN 1 144#define BLUE 2 145#define TRANSP 3 146 147#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ 148#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ 149#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ 150#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ 151 152#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) 153#define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negtive edge sampling */ 154 155enum mxsfb_devtype { 156 MXSFB_V3, 157 MXSFB_V4, 158}; 159 160/* CPU dependent register offsets */ 161struct mxsfb_devdata { 162 unsigned transfer_count; 163 unsigned cur_buf; 164 unsigned next_buf; 165 unsigned debug0; 166 unsigned hs_wdth_mask; 167 unsigned hs_wdth_shift; 168 unsigned ipversion; 169}; 170 171struct mxsfb_info { 172 struct fb_info fb_info; 173 struct platform_device *pdev; 174 struct clk *clk; 175 struct clk *clk_axi; 176 struct clk *clk_disp_axi; 177 void __iomem *base; /* registers */ 178 unsigned allocated_size; 179 int enabled; 180 unsigned ld_intf_width; 181 unsigned dotclk_delay; 182 const struct mxsfb_devdata *devdata; 183 u32 sync; 184 struct regulator *reg_lcd; 185}; 186 187#define mxsfb_is_v3(host) (host->devdata->ipversion == 3) 188#define mxsfb_is_v4(host) (host->devdata->ipversion == 4) 189 190static const struct mxsfb_devdata mxsfb_devdata[] = { 191 [MXSFB_V3] = { 192 .transfer_count = LCDC_V3_TRANSFER_COUNT, 193 .cur_buf = LCDC_V3_CUR_BUF, 194 .next_buf = LCDC_V3_NEXT_BUF, 195 .debug0 = LCDC_V3_DEBUG0, 196 .hs_wdth_mask = 0xff, 197 .hs_wdth_shift = 24, 198 .ipversion = 3, 199 }, 200 [MXSFB_V4] = { 201 .transfer_count = LCDC_V4_TRANSFER_COUNT, 202 .cur_buf = LCDC_V4_CUR_BUF, 203 .next_buf = LCDC_V4_NEXT_BUF, 204 .debug0 = LCDC_V4_DEBUG0, 205 .hs_wdth_mask = 0x3fff, 206 .hs_wdth_shift = 18, 207 .ipversion = 4, 208 }, 209}; 210 211#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) 212 213/* mask and shift depends on architecture */ 214static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) 215{ 216 return (val & host->devdata->hs_wdth_mask) << 217 host->devdata->hs_wdth_shift; 218} 219 220static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) 221{ 222 return (val >> host->devdata->hs_wdth_shift) & 223 host->devdata->hs_wdth_mask; 224} 225 226static const struct fb_bitfield def_rgb565[] = { 227 [RED] = { 228 .offset = 11, 229 .length = 5, 230 }, 231 [GREEN] = { 232 .offset = 5, 233 .length = 6, 234 }, 235 [BLUE] = { 236 .offset = 0, 237 .length = 5, 238 }, 239 [TRANSP] = { /* no support for transparency */ 240 .length = 0, 241 } 242}; 243 244static const struct fb_bitfield def_rgb888[] = { 245 [RED] = { 246 .offset = 16, 247 .length = 8, 248 }, 249 [GREEN] = { 250 .offset = 8, 251 .length = 8, 252 }, 253 [BLUE] = { 254 .offset = 0, 255 .length = 8, 256 }, 257 [TRANSP] = { /* no support for transparency */ 258 .length = 0, 259 } 260}; 261 262static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) 263{ 264 chan &= 0xffff; 265 chan >>= 16 - bf->length; 266 return chan << bf->offset; 267} 268 269static int mxsfb_check_var(struct fb_var_screeninfo *var, 270 struct fb_info *fb_info) 271{ 272 struct mxsfb_info *host = to_imxfb_host(fb_info); 273 const struct fb_bitfield *rgb = NULL; 274 275 if (var->xres < MIN_XRES) 276 var->xres = MIN_XRES; 277 if (var->yres < MIN_YRES) 278 var->yres = MIN_YRES; 279 280 var->xres_virtual = var->xres; 281 282 var->yres_virtual = var->yres; 283 284 switch (var->bits_per_pixel) { 285 case 16: 286 /* always expect RGB 565 */ 287 rgb = def_rgb565; 288 break; 289 case 32: 290 switch (host->ld_intf_width) { 291 case STMLCDIF_8BIT: 292 pr_debug("Unsupported LCD bus width mapping\n"); 293 break; 294 case STMLCDIF_16BIT: 295 case STMLCDIF_18BIT: 296 case STMLCDIF_24BIT: 297 /* real 24 bit */ 298 rgb = def_rgb888; 299 break; 300 } 301 break; 302 default: 303 pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel); 304 return -EINVAL; 305 } 306 307 /* 308 * Copy the RGB parameters for this display 309 * from the machine specific parameters. 310 */ 311 var->red = rgb[RED]; 312 var->green = rgb[GREEN]; 313 var->blue = rgb[BLUE]; 314 var->transp = rgb[TRANSP]; 315 316 return 0; 317} 318 319static inline void mxsfb_enable_axi_clk(struct mxsfb_info *host) 320{ 321 if (host->clk_axi) 322 clk_prepare_enable(host->clk_axi); 323} 324 325static inline void mxsfb_disable_axi_clk(struct mxsfb_info *host) 326{ 327 if (host->clk_axi) 328 clk_disable_unprepare(host->clk_axi); 329} 330 331static void mxsfb_enable_controller(struct fb_info *fb_info) 332{ 333 struct mxsfb_info *host = to_imxfb_host(fb_info); 334 u32 reg; 335 int ret; 336 337 dev_dbg(&host->pdev->dev, "%s\n", __func__); 338 339 if (host->reg_lcd) { 340 ret = regulator_enable(host->reg_lcd); 341 if (ret) { 342 dev_err(&host->pdev->dev, 343 "lcd regulator enable failed: %d\n", ret); 344 return; 345 } 346 } 347 348 if (host->clk_disp_axi) 349 clk_prepare_enable(host->clk_disp_axi); 350 clk_prepare_enable(host->clk); 351 clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); 352 353 mxsfb_enable_axi_clk(host); 354 355 /* if it was disabled, re-enable the mode again */ 356 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); 357 358 /* enable the SYNC signals first, then the DMA engine */ 359 reg = readl(host->base + LCDC_VDCTRL4); 360 reg |= VDCTRL4_SYNC_SIGNALS_ON; 361 writel(reg, host->base + LCDC_VDCTRL4); 362 363 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); 364 365 host->enabled = 1; 366} 367 368static void mxsfb_disable_controller(struct fb_info *fb_info) 369{ 370 struct mxsfb_info *host = to_imxfb_host(fb_info); 371 unsigned loop; 372 u32 reg; 373 int ret; 374 375 dev_dbg(&host->pdev->dev, "%s\n", __func__); 376 377 /* 378 * Even if we disable the controller here, it will still continue 379 * until its FIFOs are running out of data 380 */ 381 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR); 382 383 loop = 1000; 384 while (loop) { 385 reg = readl(host->base + LCDC_CTRL); 386 if (!(reg & CTRL_RUN)) 387 break; 388 loop--; 389 } 390 391 reg = readl(host->base + LCDC_VDCTRL4); 392 writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4); 393 394 mxsfb_disable_axi_clk(host); 395 396 clk_disable_unprepare(host->clk); 397 if (host->clk_disp_axi) 398 clk_disable_unprepare(host->clk_disp_axi); 399 400 host->enabled = 0; 401 402 if (host->reg_lcd) { 403 ret = regulator_disable(host->reg_lcd); 404 if (ret) 405 dev_err(&host->pdev->dev, 406 "lcd regulator disable failed: %d\n", ret); 407 } 408} 409 410static int mxsfb_set_par(struct fb_info *fb_info) 411{ 412 struct mxsfb_info *host = to_imxfb_host(fb_info); 413 u32 ctrl, vdctrl0, vdctrl4; 414 int line_size, fb_size; 415 int reenable = 0; 416 417 line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); 418 fb_size = fb_info->var.yres_virtual * line_size; 419 420 if (fb_size > fb_info->fix.smem_len) 421 return -ENOMEM; 422 423 fb_info->fix.line_length = line_size; 424 425 /* 426 * It seems, you can't re-program the controller if it is still running. 427 * This may lead into shifted pictures (FIFO issue?). 428 * So, first stop the controller and drain its FIFOs 429 */ 430 if (host->enabled) { 431 reenable = 1; 432 mxsfb_disable_controller(fb_info); 433 } 434 435 mxsfb_enable_axi_clk(host); 436 437 /* clear the FIFOs */ 438 writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); 439 440 ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | 441 CTRL_SET_BUS_WIDTH(host->ld_intf_width); 442 443 switch (fb_info->var.bits_per_pixel) { 444 case 16: 445 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); 446 ctrl |= CTRL_SET_WORD_LENGTH(0); 447 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1); 448 break; 449 case 32: 450 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); 451 ctrl |= CTRL_SET_WORD_LENGTH(3); 452 switch (host->ld_intf_width) { 453 case STMLCDIF_8BIT: 454 mxsfb_disable_axi_clk(host); 455 dev_err(&host->pdev->dev, 456 "Unsupported LCD bus width mapping\n"); 457 return -EINVAL; 458 case STMLCDIF_16BIT: 459 case STMLCDIF_18BIT: 460 case STMLCDIF_24BIT: 461 /* real 24 bit */ 462 break; 463 } 464 /* do not use packed pixels = one pixel per word instead */ 465 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); 466 break; 467 default: 468 mxsfb_disable_axi_clk(host); 469 dev_err(&host->pdev->dev, "Unhandled color depth of %u\n", 470 fb_info->var.bits_per_pixel); 471 return -EINVAL; 472 } 473 474 writel(ctrl, host->base + LCDC_CTRL); 475 476 writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | 477 TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), 478 host->base + host->devdata->transfer_count); 479 480 vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ 481 VDCTRL0_VSYNC_PERIOD_UNIT | 482 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | 483 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); 484 if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) 485 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; 486 if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) 487 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; 488 if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT) 489 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; 490 if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT) 491 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING; 492 493 writel(vdctrl0, host->base + LCDC_VDCTRL0); 494 495 /* frame length in lines */ 496 writel(fb_info->var.upper_margin + fb_info->var.vsync_len + 497 fb_info->var.lower_margin + fb_info->var.yres, 498 host->base + LCDC_VDCTRL1); 499 500 /* line length in units of clocks or pixels */ 501 writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | 502 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + 503 fb_info->var.hsync_len + fb_info->var.right_margin + 504 fb_info->var.xres), 505 host->base + LCDC_VDCTRL2); 506 507 writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + 508 fb_info->var.hsync_len) | 509 SET_VERT_WAIT_CNT(fb_info->var.upper_margin + 510 fb_info->var.vsync_len), 511 host->base + LCDC_VDCTRL3); 512 513 vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); 514 if (mxsfb_is_v4(host)) 515 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); 516 writel(vdctrl4, host->base + LCDC_VDCTRL4); 517 518 writel(fb_info->fix.smem_start + 519 fb_info->fix.line_length * fb_info->var.yoffset, 520 host->base + host->devdata->next_buf); 521 522 mxsfb_disable_axi_clk(host); 523 524 if (reenable) 525 mxsfb_enable_controller(fb_info); 526 527 return 0; 528} 529 530static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 531 u_int transp, struct fb_info *fb_info) 532{ 533 unsigned int val; 534 int ret = -EINVAL; 535 536 /* 537 * If greyscale is true, then we convert the RGB value 538 * to greyscale no matter what visual we are using. 539 */ 540 if (fb_info->var.grayscale) 541 red = green = blue = (19595 * red + 38470 * green + 542 7471 * blue) >> 16; 543 544 switch (fb_info->fix.visual) { 545 case FB_VISUAL_TRUECOLOR: 546 /* 547 * 12 or 16-bit True Colour. We encode the RGB value 548 * according to the RGB bitfield information. 549 */ 550 if (regno < 16) { 551 u32 *pal = fb_info->pseudo_palette; 552 553 val = chan_to_field(red, &fb_info->var.red); 554 val |= chan_to_field(green, &fb_info->var.green); 555 val |= chan_to_field(blue, &fb_info->var.blue); 556 557 pal[regno] = val; 558 ret = 0; 559 } 560 break; 561 562 case FB_VISUAL_STATIC_PSEUDOCOLOR: 563 case FB_VISUAL_PSEUDOCOLOR: 564 break; 565 } 566 567 return ret; 568} 569 570static int mxsfb_blank(int blank, struct fb_info *fb_info) 571{ 572 struct mxsfb_info *host = to_imxfb_host(fb_info); 573 574 switch (blank) { 575 case FB_BLANK_POWERDOWN: 576 case FB_BLANK_VSYNC_SUSPEND: 577 case FB_BLANK_HSYNC_SUSPEND: 578 case FB_BLANK_NORMAL: 579 if (host->enabled) 580 mxsfb_disable_controller(fb_info); 581 break; 582 583 case FB_BLANK_UNBLANK: 584 if (!host->enabled) 585 mxsfb_enable_controller(fb_info); 586 break; 587 } 588 return 0; 589} 590 591static int mxsfb_pan_display(struct fb_var_screeninfo *var, 592 struct fb_info *fb_info) 593{ 594 struct mxsfb_info *host = to_imxfb_host(fb_info); 595 unsigned offset; 596 597 if (var->xoffset != 0) 598 return -EINVAL; 599 600 offset = fb_info->fix.line_length * var->yoffset; 601 602 mxsfb_enable_axi_clk(host); 603 604 /* update on next VSYNC */ 605 writel(fb_info->fix.smem_start + offset, 606 host->base + host->devdata->next_buf); 607 608 mxsfb_disable_axi_clk(host); 609 610 return 0; 611} 612 613static struct fb_ops mxsfb_ops = { 614 .owner = THIS_MODULE, 615 .fb_check_var = mxsfb_check_var, 616 .fb_set_par = mxsfb_set_par, 617 .fb_setcolreg = mxsfb_setcolreg, 618 .fb_blank = mxsfb_blank, 619 .fb_pan_display = mxsfb_pan_display, 620 .fb_fillrect = cfb_fillrect, 621 .fb_copyarea = cfb_copyarea, 622 .fb_imageblit = cfb_imageblit, 623}; 624 625static int mxsfb_restore_mode(struct mxsfb_info *host, 626 struct fb_videomode *vmode) 627{ 628 struct fb_info *fb_info = &host->fb_info; 629 unsigned line_count; 630 unsigned period; 631 unsigned long pa, fbsize; 632 int bits_per_pixel, ofs, ret = 0; 633 u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; 634 635 mxsfb_enable_axi_clk(host); 636 637 /* Only restore the mode when the controller is running */ 638 ctrl = readl(host->base + LCDC_CTRL); 639 if (!(ctrl & CTRL_RUN)) { 640 ret = -EINVAL; 641 goto err; 642 } 643 644 vdctrl0 = readl(host->base + LCDC_VDCTRL0); 645 vdctrl2 = readl(host->base + LCDC_VDCTRL2); 646 vdctrl3 = readl(host->base + LCDC_VDCTRL3); 647 vdctrl4 = readl(host->base + LCDC_VDCTRL4); 648 649 transfer_count = readl(host->base + host->devdata->transfer_count); 650 651 vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); 652 vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); 653 654 switch (CTRL_GET_WORD_LENGTH(ctrl)) { 655 case 0: 656 bits_per_pixel = 16; 657 break; 658 case 3: 659 bits_per_pixel = 32; 660 break; 661 case 1: 662 default: 663 ret = -EINVAL; 664 goto err; 665 } 666 667 fb_info->var.bits_per_pixel = bits_per_pixel; 668 669 vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); 670 vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2); 671 vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len; 672 vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - 673 vmode->hsync_len - vmode->left_margin - vmode->xres; 674 vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); 675 period = readl(host->base + LCDC_VDCTRL1); 676 vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len; 677 vmode->lower_margin = period - vmode->vsync_len - 678 vmode->upper_margin - vmode->yres; 679 680 vmode->vmode = FB_VMODE_NONINTERLACED; 681 682 vmode->sync = 0; 683 if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) 684 vmode->sync |= FB_SYNC_HOR_HIGH_ACT; 685 if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) 686 vmode->sync |= FB_SYNC_VERT_HIGH_ACT; 687 688 pr_debug("Reconstructed video mode:\n"); 689 pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", 690 vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin, 691 vmode->right_margin, vmode->vsync_len, vmode->upper_margin, 692 vmode->lower_margin); 693 pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock)); 694 695 host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); 696 host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); 697 698 fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3); 699 700 pa = readl(host->base + host->devdata->cur_buf); 701 fbsize = fb_info->fix.line_length * vmode->yres; 702 if (pa < fb_info->fix.smem_start) { 703 ret = -EINVAL; 704 goto err; 705 } 706 if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) { 707 ret = -EINVAL; 708 goto err; 709 } 710 ofs = pa - fb_info->fix.smem_start; 711 if (ofs) { 712 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); 713 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); 714 } 715 716 line_count = fb_info->fix.smem_len / fb_info->fix.line_length; 717 fb_info->fix.ypanstep = 1; 718 719 clk_prepare_enable(host->clk); 720 host->enabled = 1; 721 722err: 723 if (ret) 724 mxsfb_disable_axi_clk(host); 725 726 return ret; 727} 728 729static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host, 730 struct fb_videomode *vmode) 731{ 732 struct fb_info *fb_info = &host->fb_info; 733 struct fb_var_screeninfo *var = &fb_info->var; 734 struct device *dev = &host->pdev->dev; 735 struct device_node *np = host->pdev->dev.of_node; 736 struct device_node *display_np; 737 struct videomode vm; 738 u32 width; 739 int ret; 740 741 display_np = of_parse_phandle(np, "display", 0); 742 if (!display_np) { 743 dev_err(dev, "failed to find display phandle\n"); 744 return -ENOENT; 745 } 746 747 ret = of_property_read_u32(display_np, "bus-width", &width); 748 if (ret < 0) { 749 dev_err(dev, "failed to get property bus-width\n"); 750 goto put_display_node; 751 } 752 753 switch (width) { 754 case 8: 755 host->ld_intf_width = STMLCDIF_8BIT; 756 break; 757 case 16: 758 host->ld_intf_width = STMLCDIF_16BIT; 759 break; 760 case 18: 761 host->ld_intf_width = STMLCDIF_18BIT; 762 break; 763 case 24: 764 host->ld_intf_width = STMLCDIF_24BIT; 765 break; 766 default: 767 dev_err(dev, "invalid bus-width value\n"); 768 ret = -EINVAL; 769 goto put_display_node; 770 } 771 772 ret = of_property_read_u32(display_np, "bits-per-pixel", 773 &var->bits_per_pixel); 774 if (ret < 0) { 775 dev_err(dev, "failed to get property bits-per-pixel\n"); 776 goto put_display_node; 777 } 778 779 ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE); 780 if (ret) { 781 dev_err(dev, "failed to get videomode from DT\n"); 782 goto put_display_node; 783 } 784 785 ret = fb_videomode_from_videomode(&vm, vmode); 786 if (ret < 0) 787 goto put_display_node; 788 789 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 790 host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; 791 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 792 host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT; 793 794put_display_node: 795 of_node_put(display_np); 796 return ret; 797} 798 799static int mxsfb_init_fbinfo(struct mxsfb_info *host, 800 struct fb_videomode *vmode) 801{ 802 int ret; 803 struct fb_info *fb_info = &host->fb_info; 804 struct fb_var_screeninfo *var = &fb_info->var; 805 dma_addr_t fb_phys; 806 void *fb_virt; 807 unsigned fb_size; 808 809 fb_info->fbops = &mxsfb_ops; 810 fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; 811 strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); 812 fb_info->fix.type = FB_TYPE_PACKED_PIXELS; 813 fb_info->fix.ypanstep = 1; 814 fb_info->fix.visual = FB_VISUAL_TRUECOLOR, 815 fb_info->fix.accel = FB_ACCEL_NONE; 816 817 ret = mxsfb_init_fbinfo_dt(host, vmode); 818 if (ret) 819 return ret; 820 821 var->nonstd = 0; 822 var->activate = FB_ACTIVATE_NOW; 823 var->accel_flags = 0; 824 var->vmode = FB_VMODE_NONINTERLACED; 825 826 /* Memory allocation for framebuffer */ 827 fb_size = SZ_2M; 828 fb_virt = alloc_pages_exact(fb_size, GFP_DMA); 829 if (!fb_virt) 830 return -ENOMEM; 831 832 fb_phys = virt_to_phys(fb_virt); 833 834 fb_info->fix.smem_start = fb_phys; 835 fb_info->screen_base = fb_virt; 836 fb_info->screen_size = fb_info->fix.smem_len = fb_size; 837 838 if (mxsfb_restore_mode(host, vmode)) 839 memset(fb_virt, 0, fb_size); 840 841 return 0; 842} 843 844static void mxsfb_free_videomem(struct mxsfb_info *host) 845{ 846 struct fb_info *fb_info = &host->fb_info; 847 848 free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); 849} 850 851static struct platform_device_id mxsfb_devtype[] = { 852 { 853 .name = "imx23-fb", 854 .driver_data = MXSFB_V3, 855 }, { 856 .name = "imx28-fb", 857 .driver_data = MXSFB_V4, 858 }, { 859 /* sentinel */ 860 } 861}; 862MODULE_DEVICE_TABLE(platform, mxsfb_devtype); 863 864static const struct of_device_id mxsfb_dt_ids[] = { 865 { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], }, 866 { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], }, 867 { /* sentinel */ } 868}; 869MODULE_DEVICE_TABLE(of, mxsfb_dt_ids); 870 871static int mxsfb_probe(struct platform_device *pdev) 872{ 873 const struct of_device_id *of_id = 874 of_match_device(mxsfb_dt_ids, &pdev->dev); 875 struct resource *res; 876 struct mxsfb_info *host; 877 struct fb_info *fb_info; 878 struct fb_videomode *mode; 879 int ret; 880 881 if (of_id) 882 pdev->id_entry = of_id->data; 883 884 fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); 885 if (!fb_info) { 886 dev_err(&pdev->dev, "Failed to allocate fbdev\n"); 887 return -ENOMEM; 888 } 889 890 mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode), 891 GFP_KERNEL); 892 if (mode == NULL) 893 return -ENOMEM; 894 895 host = to_imxfb_host(fb_info); 896 897 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 898 host->base = devm_ioremap_resource(&pdev->dev, res); 899 if (IS_ERR(host->base)) { 900 ret = PTR_ERR(host->base); 901 goto fb_release; 902 } 903 904 host->pdev = pdev; 905 platform_set_drvdata(pdev, host); 906 907 host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; 908 909 host->clk = devm_clk_get(&host->pdev->dev, NULL); 910 if (IS_ERR(host->clk)) { 911 ret = PTR_ERR(host->clk); 912 goto fb_release; 913 } 914 915 host->clk_axi = devm_clk_get(&host->pdev->dev, "axi"); 916 if (IS_ERR(host->clk_axi)) 917 host->clk_axi = NULL; 918 919 host->clk_disp_axi = devm_clk_get(&host->pdev->dev, "disp_axi"); 920 if (IS_ERR(host->clk_disp_axi)) 921 host->clk_disp_axi = NULL; 922 923 host->reg_lcd = devm_regulator_get(&pdev->dev, "lcd"); 924 if (IS_ERR(host->reg_lcd)) 925 host->reg_lcd = NULL; 926 927 fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16, 928 GFP_KERNEL); 929 if (!fb_info->pseudo_palette) { 930 ret = -ENOMEM; 931 goto fb_release; 932 } 933 934 ret = mxsfb_init_fbinfo(host, mode); 935 if (ret != 0) 936 goto fb_release; 937 938 fb_videomode_to_var(&fb_info->var, mode); 939 940 /* init the color fields */ 941 mxsfb_check_var(&fb_info->var, fb_info); 942 943 platform_set_drvdata(pdev, fb_info); 944 945 ret = register_framebuffer(fb_info); 946 if (ret != 0) { 947 dev_err(&pdev->dev,"Failed to register framebuffer\n"); 948 goto fb_destroy; 949 } 950 951 if (!host->enabled) { 952 mxsfb_enable_axi_clk(host); 953 writel(0, host->base + LCDC_CTRL); 954 mxsfb_disable_axi_clk(host); 955 mxsfb_set_par(fb_info); 956 mxsfb_enable_controller(fb_info); 957 } 958 959 dev_info(&pdev->dev, "initialized\n"); 960 961 return 0; 962 963fb_destroy: 964 if (host->enabled) 965 clk_disable_unprepare(host->clk); 966fb_release: 967 framebuffer_release(fb_info); 968 969 return ret; 970} 971 972static int mxsfb_remove(struct platform_device *pdev) 973{ 974 struct fb_info *fb_info = platform_get_drvdata(pdev); 975 struct mxsfb_info *host = to_imxfb_host(fb_info); 976 977 if (host->enabled) 978 mxsfb_disable_controller(fb_info); 979 980 unregister_framebuffer(fb_info); 981 mxsfb_free_videomem(host); 982 983 framebuffer_release(fb_info); 984 985 return 0; 986} 987 988static void mxsfb_shutdown(struct platform_device *pdev) 989{ 990 struct fb_info *fb_info = platform_get_drvdata(pdev); 991 struct mxsfb_info *host = to_imxfb_host(fb_info); 992 993 mxsfb_enable_axi_clk(host); 994 995 /* 996 * Force stop the LCD controller as keeping it running during reboot 997 * might interfere with the BootROM's boot mode pads sampling. 998 */ 999 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR); 1000 1001 mxsfb_disable_axi_clk(host); 1002} 1003 1004static struct platform_driver mxsfb_driver = { 1005 .probe = mxsfb_probe, 1006 .remove = mxsfb_remove, 1007 .shutdown = mxsfb_shutdown, 1008 .id_table = mxsfb_devtype, 1009 .driver = { 1010 .name = DRIVER_NAME, 1011 .of_match_table = mxsfb_dt_ids, 1012 }, 1013}; 1014 1015module_platform_driver(mxsfb_driver); 1016 1017MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); 1018MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1019MODULE_LICENSE("GPL"); 1020