1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36
37 #include <linux/usb.h>
38 #include <linux/usb/otg.h>
39 #include <linux/usb/of.h>
40 #include <linux/usb/ulpi.h>
41 #include <linux/usb/gadget.h>
42 #include <linux/usb/hcd.h>
43 #include <linux/usb/msm_hsusb.h>
44 #include <linux/usb/msm_hsusb_hw.h>
45 #include <linux/regulator/consumer.h>
46
47 #define MSM_USB_BASE (motg->regs)
48 #define DRIVER_NAME "msm_otg"
49
50 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
51 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
52
53 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
54 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
55 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
56 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
57
58 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
59 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
60 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
61 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
62
63 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
64 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
65 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
66
67 enum vdd_levels {
68 VDD_LEVEL_NONE = 0,
69 VDD_LEVEL_MIN,
70 VDD_LEVEL_MAX,
71 };
72
msm_hsusb_init_vddcx(struct msm_otg * motg,int init)73 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
74 {
75 int ret = 0;
76
77 if (init) {
78 ret = regulator_set_voltage(motg->vddcx,
79 motg->vdd_levels[VDD_LEVEL_MIN],
80 motg->vdd_levels[VDD_LEVEL_MAX]);
81 if (ret) {
82 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
83 return ret;
84 }
85
86 ret = regulator_enable(motg->vddcx);
87 if (ret)
88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
89 } else {
90 ret = regulator_set_voltage(motg->vddcx, 0,
91 motg->vdd_levels[VDD_LEVEL_MAX]);
92 if (ret)
93 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
94 ret = regulator_disable(motg->vddcx);
95 if (ret)
96 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
97 }
98
99 return ret;
100 }
101
msm_hsusb_ldo_init(struct msm_otg * motg,int init)102 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
103 {
104 int rc = 0;
105
106 if (init) {
107 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
108 USB_PHY_3P3_VOL_MAX);
109 if (rc) {
110 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
111 goto exit;
112 }
113 rc = regulator_enable(motg->v3p3);
114 if (rc) {
115 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
116 goto exit;
117 }
118 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
119 USB_PHY_1P8_VOL_MAX);
120 if (rc) {
121 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
122 goto disable_3p3;
123 }
124 rc = regulator_enable(motg->v1p8);
125 if (rc) {
126 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
127 goto disable_3p3;
128 }
129
130 return 0;
131 }
132
133 regulator_disable(motg->v1p8);
134 disable_3p3:
135 regulator_disable(motg->v3p3);
136 exit:
137 return rc;
138 }
139
msm_hsusb_ldo_set_mode(struct msm_otg * motg,int on)140 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
141 {
142 int ret = 0;
143
144 if (on) {
145 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
146 if (ret < 0) {
147 pr_err("Could not set HPM for v1p8\n");
148 return ret;
149 }
150 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
151 if (ret < 0) {
152 pr_err("Could not set HPM for v3p3\n");
153 regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
154 return ret;
155 }
156 } else {
157 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
158 if (ret < 0)
159 pr_err("Could not set LPM for v1p8\n");
160 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
161 if (ret < 0)
162 pr_err("Could not set LPM for v3p3\n");
163 }
164
165 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
166 return ret < 0 ? ret : 0;
167 }
168
ulpi_read(struct usb_phy * phy,u32 reg)169 static int ulpi_read(struct usb_phy *phy, u32 reg)
170 {
171 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
172 int cnt = 0;
173
174 /* initiate read operation */
175 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
176 USB_ULPI_VIEWPORT);
177
178 /* wait for completion */
179 while (cnt < ULPI_IO_TIMEOUT_USEC) {
180 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
181 break;
182 udelay(1);
183 cnt++;
184 }
185
186 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
187 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
188 readl(USB_ULPI_VIEWPORT));
189 return -ETIMEDOUT;
190 }
191 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
192 }
193
ulpi_write(struct usb_phy * phy,u32 val,u32 reg)194 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
195 {
196 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
197 int cnt = 0;
198
199 /* initiate write operation */
200 writel(ULPI_RUN | ULPI_WRITE |
201 ULPI_ADDR(reg) | ULPI_DATA(val),
202 USB_ULPI_VIEWPORT);
203
204 /* wait for completion */
205 while (cnt < ULPI_IO_TIMEOUT_USEC) {
206 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
207 break;
208 udelay(1);
209 cnt++;
210 }
211
212 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
213 dev_err(phy->dev, "ulpi_write: timeout\n");
214 return -ETIMEDOUT;
215 }
216 return 0;
217 }
218
219 static struct usb_phy_io_ops msm_otg_io_ops = {
220 .read = ulpi_read,
221 .write = ulpi_write,
222 };
223
ulpi_init(struct msm_otg * motg)224 static void ulpi_init(struct msm_otg *motg)
225 {
226 struct msm_otg_platform_data *pdata = motg->pdata;
227 int *seq = pdata->phy_init_seq, idx;
228 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
229
230 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
231 if (seq[idx] == -1)
232 continue;
233
234 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
235 seq[idx], addr + idx);
236 ulpi_write(&motg->phy, seq[idx], addr + idx);
237 }
238 }
239
msm_phy_notify_disconnect(struct usb_phy * phy,enum usb_device_speed speed)240 static int msm_phy_notify_disconnect(struct usb_phy *phy,
241 enum usb_device_speed speed)
242 {
243 int val;
244
245 /*
246 * Put the transceiver in non-driving mode. Otherwise host
247 * may not detect soft-disconnection.
248 */
249 val = ulpi_read(phy, ULPI_FUNC_CTRL);
250 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
251 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
252 ulpi_write(phy, val, ULPI_FUNC_CTRL);
253
254 return 0;
255 }
256
msm_otg_link_clk_reset(struct msm_otg * motg,bool assert)257 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
258 {
259 int ret;
260
261 if (assert)
262 ret = reset_control_assert(motg->link_rst);
263 else
264 ret = reset_control_deassert(motg->link_rst);
265
266 if (ret)
267 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
268 assert ? "assert" : "deassert");
269
270 return ret;
271 }
272
msm_otg_phy_clk_reset(struct msm_otg * motg)273 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
274 {
275 int ret = 0;
276
277 if (motg->phy_rst)
278 ret = reset_control_reset(motg->phy_rst);
279
280 if (ret)
281 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
282
283 return ret;
284 }
285
msm_link_reset(struct msm_otg * motg)286 static int msm_link_reset(struct msm_otg *motg)
287 {
288 u32 val;
289 int ret;
290
291 ret = msm_otg_link_clk_reset(motg, 1);
292 if (ret)
293 return ret;
294
295 /* wait for 1ms delay as suggested in HPG. */
296 usleep_range(1000, 1200);
297
298 ret = msm_otg_link_clk_reset(motg, 0);
299 if (ret)
300 return ret;
301
302 if (motg->phy_number)
303 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
304
305 /* put transceiver in serial mode as part of reset */
306 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
307 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
308
309 return 0;
310 }
311
msm_otg_reset(struct usb_phy * phy)312 static int msm_otg_reset(struct usb_phy *phy)
313 {
314 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
315 int cnt = 0;
316
317 writel(USBCMD_RESET, USB_USBCMD);
318 while (cnt < LINK_RESET_TIMEOUT_USEC) {
319 if (!(readl(USB_USBCMD) & USBCMD_RESET))
320 break;
321 udelay(1);
322 cnt++;
323 }
324 if (cnt >= LINK_RESET_TIMEOUT_USEC)
325 return -ETIMEDOUT;
326
327 /* select ULPI phy and clear other status/control bits in PORTSC */
328 writel(PORTSC_PTS_ULPI, USB_PORTSC);
329
330 writel(0x0, USB_AHBBURST);
331 writel(0x08, USB_AHBMODE);
332
333 if (motg->phy_number)
334 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
335 return 0;
336 }
337
msm_phy_reset(struct msm_otg * motg)338 static void msm_phy_reset(struct msm_otg *motg)
339 {
340 void __iomem *addr;
341
342 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
343 msm_otg_phy_clk_reset(motg);
344 return;
345 }
346
347 addr = USB_PHY_CTRL;
348 if (motg->phy_number)
349 addr = USB_PHY_CTRL2;
350
351 /* Assert USB PHY_POR */
352 writel(readl(addr) | PHY_POR_ASSERT, addr);
353
354 /*
355 * wait for minimum 10 microseconds as suggested in HPG.
356 * Use a slightly larger value since the exact value didn't
357 * work 100% of the time.
358 */
359 udelay(12);
360
361 /* Deassert USB PHY_POR */
362 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
363 }
364
msm_usb_reset(struct usb_phy * phy)365 static int msm_usb_reset(struct usb_phy *phy)
366 {
367 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
368 int ret;
369
370 if (!IS_ERR(motg->core_clk))
371 clk_prepare_enable(motg->core_clk);
372
373 ret = msm_link_reset(motg);
374 if (ret) {
375 dev_err(phy->dev, "phy_reset failed\n");
376 return ret;
377 }
378
379 ret = msm_otg_reset(&motg->phy);
380 if (ret) {
381 dev_err(phy->dev, "link reset failed\n");
382 return ret;
383 }
384
385 msleep(100);
386
387 /* Reset USB PHY after performing USB Link RESET */
388 msm_phy_reset(motg);
389
390 if (!IS_ERR(motg->core_clk))
391 clk_disable_unprepare(motg->core_clk);
392
393 return 0;
394 }
395
msm_phy_init(struct usb_phy * phy)396 static int msm_phy_init(struct usb_phy *phy)
397 {
398 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
399 struct msm_otg_platform_data *pdata = motg->pdata;
400 u32 val, ulpi_val = 0;
401
402 /* Program USB PHY Override registers. */
403 ulpi_init(motg);
404
405 /*
406 * It is recommended in HPG to reset USB PHY after programming
407 * USB PHY Override registers.
408 */
409 msm_phy_reset(motg);
410
411 if (pdata->otg_control == OTG_PHY_CONTROL) {
412 val = readl(USB_OTGSC);
413 if (pdata->mode == USB_DR_MODE_OTG) {
414 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
415 val |= OTGSC_IDIE | OTGSC_BSVIE;
416 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
417 ulpi_val = ULPI_INT_SESS_VALID;
418 val |= OTGSC_BSVIE;
419 }
420 writel(val, USB_OTGSC);
421 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
422 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
423 }
424
425 if (motg->phy_number)
426 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
427
428 return 0;
429 }
430
431 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
432 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
433
434 #ifdef CONFIG_PM
435
msm_hsusb_config_vddcx(struct msm_otg * motg,int high)436 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
437 {
438 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
439 int min_vol;
440 int ret;
441
442 if (high)
443 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
444 else
445 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
446
447 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
448 if (ret) {
449 pr_err("Cannot set vddcx voltage\n");
450 return ret;
451 }
452
453 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
454
455 return ret;
456 }
457
msm_otg_suspend(struct msm_otg * motg)458 static int msm_otg_suspend(struct msm_otg *motg)
459 {
460 struct usb_phy *phy = &motg->phy;
461 struct usb_bus *bus = phy->otg->host;
462 struct msm_otg_platform_data *pdata = motg->pdata;
463 void __iomem *addr;
464 int cnt = 0;
465
466 if (atomic_read(&motg->in_lpm))
467 return 0;
468
469 disable_irq(motg->irq);
470 /*
471 * Chipidea 45-nm PHY suspend sequence:
472 *
473 * Interrupt Latch Register auto-clear feature is not present
474 * in all PHY versions. Latch register is clear on read type.
475 * Clear latch register to avoid spurious wakeup from
476 * low power mode (LPM).
477 *
478 * PHY comparators are disabled when PHY enters into low power
479 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
480 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
481 * PHY comparators. This save significant amount of power.
482 *
483 * PLL is not turned off when PHY enters into low power mode (LPM).
484 * Disable PLL for maximum power savings.
485 */
486
487 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
488 ulpi_read(phy, 0x14);
489 if (pdata->otg_control == OTG_PHY_CONTROL)
490 ulpi_write(phy, 0x01, 0x30);
491 ulpi_write(phy, 0x08, 0x09);
492 }
493
494 /*
495 * PHY may take some time or even fail to enter into low power
496 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
497 * in failure case.
498 */
499 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
500 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
501 if (readl(USB_PORTSC) & PORTSC_PHCD)
502 break;
503 udelay(1);
504 cnt++;
505 }
506
507 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
508 dev_err(phy->dev, "Unable to suspend PHY\n");
509 msm_otg_reset(phy);
510 enable_irq(motg->irq);
511 return -ETIMEDOUT;
512 }
513
514 /*
515 * PHY has capability to generate interrupt asynchronously in low
516 * power mode (LPM). This interrupt is level triggered. So USB IRQ
517 * line must be disabled till async interrupt enable bit is cleared
518 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
519 * block data communication from PHY.
520 */
521 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
522
523 addr = USB_PHY_CTRL;
524 if (motg->phy_number)
525 addr = USB_PHY_CTRL2;
526
527 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
528 motg->pdata->otg_control == OTG_PMIC_CONTROL)
529 writel(readl(addr) | PHY_RETEN, addr);
530
531 clk_disable_unprepare(motg->pclk);
532 clk_disable_unprepare(motg->clk);
533 if (!IS_ERR(motg->core_clk))
534 clk_disable_unprepare(motg->core_clk);
535
536 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
537 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
538 msm_hsusb_ldo_set_mode(motg, 0);
539 msm_hsusb_config_vddcx(motg, 0);
540 }
541
542 if (device_may_wakeup(phy->dev))
543 enable_irq_wake(motg->irq);
544 if (bus)
545 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
546
547 atomic_set(&motg->in_lpm, 1);
548 enable_irq(motg->irq);
549
550 dev_info(phy->dev, "USB in low power mode\n");
551
552 return 0;
553 }
554
msm_otg_resume(struct msm_otg * motg)555 static int msm_otg_resume(struct msm_otg *motg)
556 {
557 struct usb_phy *phy = &motg->phy;
558 struct usb_bus *bus = phy->otg->host;
559 void __iomem *addr;
560 int cnt = 0;
561 unsigned temp;
562
563 if (!atomic_read(&motg->in_lpm))
564 return 0;
565
566 clk_prepare_enable(motg->pclk);
567 clk_prepare_enable(motg->clk);
568 if (!IS_ERR(motg->core_clk))
569 clk_prepare_enable(motg->core_clk);
570
571 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
572 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
573
574 addr = USB_PHY_CTRL;
575 if (motg->phy_number)
576 addr = USB_PHY_CTRL2;
577
578 msm_hsusb_ldo_set_mode(motg, 1);
579 msm_hsusb_config_vddcx(motg, 1);
580 writel(readl(addr) & ~PHY_RETEN, addr);
581 }
582
583 temp = readl(USB_USBCMD);
584 temp &= ~ASYNC_INTR_CTRL;
585 temp &= ~ULPI_STP_CTRL;
586 writel(temp, USB_USBCMD);
587
588 /*
589 * PHY comes out of low power mode (LPM) in case of wakeup
590 * from asynchronous interrupt.
591 */
592 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
593 goto skip_phy_resume;
594
595 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
596 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
597 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
598 break;
599 udelay(1);
600 cnt++;
601 }
602
603 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
604 /*
605 * This is a fatal error. Reset the link and
606 * PHY. USB state can not be restored. Re-insertion
607 * of USB cable is the only way to get USB working.
608 */
609 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
610 msm_otg_reset(phy);
611 }
612
613 skip_phy_resume:
614 if (device_may_wakeup(phy->dev))
615 disable_irq_wake(motg->irq);
616 if (bus)
617 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
618
619 atomic_set(&motg->in_lpm, 0);
620
621 if (motg->async_int) {
622 motg->async_int = 0;
623 pm_runtime_put(phy->dev);
624 enable_irq(motg->irq);
625 }
626
627 dev_info(phy->dev, "USB exited from low power mode\n");
628
629 return 0;
630 }
631 #endif
632
msm_otg_notify_charger(struct msm_otg * motg,unsigned mA)633 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
634 {
635 if (motg->cur_power == mA)
636 return;
637
638 /* TODO: Notify PMIC about available current */
639 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
640 motg->cur_power = mA;
641 }
642
msm_otg_set_power(struct usb_phy * phy,unsigned mA)643 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
644 {
645 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
646
647 /*
648 * Gadget driver uses set_power method to notify about the
649 * available current based on suspend/configured states.
650 *
651 * IDEV_CHG can be drawn irrespective of suspend/un-configured
652 * states when CDP/ACA is connected.
653 */
654 if (motg->chg_type == USB_SDP_CHARGER)
655 msm_otg_notify_charger(motg, mA);
656
657 return 0;
658 }
659
msm_otg_start_host(struct usb_phy * phy,int on)660 static void msm_otg_start_host(struct usb_phy *phy, int on)
661 {
662 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
663 struct msm_otg_platform_data *pdata = motg->pdata;
664 struct usb_hcd *hcd;
665
666 if (!phy->otg->host)
667 return;
668
669 hcd = bus_to_hcd(phy->otg->host);
670
671 if (on) {
672 dev_dbg(phy->dev, "host on\n");
673
674 if (pdata->vbus_power)
675 pdata->vbus_power(1);
676 /*
677 * Some boards have a switch cotrolled by gpio
678 * to enable/disable internal HUB. Enable internal
679 * HUB before kicking the host.
680 */
681 if (pdata->setup_gpio)
682 pdata->setup_gpio(OTG_STATE_A_HOST);
683 #ifdef CONFIG_USB
684 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
685 device_wakeup_enable(hcd->self.controller);
686 #endif
687 } else {
688 dev_dbg(phy->dev, "host off\n");
689
690 #ifdef CONFIG_USB
691 usb_remove_hcd(hcd);
692 #endif
693 if (pdata->setup_gpio)
694 pdata->setup_gpio(OTG_STATE_UNDEFINED);
695 if (pdata->vbus_power)
696 pdata->vbus_power(0);
697 }
698 }
699
msm_otg_set_host(struct usb_otg * otg,struct usb_bus * host)700 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
701 {
702 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
703 struct usb_hcd *hcd;
704
705 /*
706 * Fail host registration if this board can support
707 * only peripheral configuration.
708 */
709 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
710 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
711 return -ENODEV;
712 }
713
714 if (!host) {
715 if (otg->state == OTG_STATE_A_HOST) {
716 pm_runtime_get_sync(otg->usb_phy->dev);
717 msm_otg_start_host(otg->usb_phy, 0);
718 otg->host = NULL;
719 otg->state = OTG_STATE_UNDEFINED;
720 schedule_work(&motg->sm_work);
721 } else {
722 otg->host = NULL;
723 }
724
725 return 0;
726 }
727
728 hcd = bus_to_hcd(host);
729 hcd->power_budget = motg->pdata->power_budget;
730
731 otg->host = host;
732 dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
733
734 /*
735 * Kick the state machine work, if peripheral is not supported
736 * or peripheral is already registered with us.
737 */
738 if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
739 pm_runtime_get_sync(otg->usb_phy->dev);
740 schedule_work(&motg->sm_work);
741 }
742
743 return 0;
744 }
745
msm_otg_start_peripheral(struct usb_phy * phy,int on)746 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
747 {
748 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
749 struct msm_otg_platform_data *pdata = motg->pdata;
750
751 if (!phy->otg->gadget)
752 return;
753
754 if (on) {
755 dev_dbg(phy->dev, "gadget on\n");
756 /*
757 * Some boards have a switch cotrolled by gpio
758 * to enable/disable internal HUB. Disable internal
759 * HUB before kicking the gadget.
760 */
761 if (pdata->setup_gpio)
762 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
763 usb_gadget_vbus_connect(phy->otg->gadget);
764 } else {
765 dev_dbg(phy->dev, "gadget off\n");
766 usb_gadget_vbus_disconnect(phy->otg->gadget);
767 if (pdata->setup_gpio)
768 pdata->setup_gpio(OTG_STATE_UNDEFINED);
769 }
770
771 }
772
msm_otg_set_peripheral(struct usb_otg * otg,struct usb_gadget * gadget)773 static int msm_otg_set_peripheral(struct usb_otg *otg,
774 struct usb_gadget *gadget)
775 {
776 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
777
778 /*
779 * Fail peripheral registration if this board can support
780 * only host configuration.
781 */
782 if (motg->pdata->mode == USB_DR_MODE_HOST) {
783 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
784 return -ENODEV;
785 }
786
787 if (!gadget) {
788 if (otg->state == OTG_STATE_B_PERIPHERAL) {
789 pm_runtime_get_sync(otg->usb_phy->dev);
790 msm_otg_start_peripheral(otg->usb_phy, 0);
791 otg->gadget = NULL;
792 otg->state = OTG_STATE_UNDEFINED;
793 schedule_work(&motg->sm_work);
794 } else {
795 otg->gadget = NULL;
796 }
797
798 return 0;
799 }
800 otg->gadget = gadget;
801 dev_dbg(otg->usb_phy->dev,
802 "peripheral driver registered w/ tranceiver\n");
803
804 /*
805 * Kick the state machine work, if host is not supported
806 * or host is already registered with us.
807 */
808 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
809 pm_runtime_get_sync(otg->usb_phy->dev);
810 schedule_work(&motg->sm_work);
811 }
812
813 return 0;
814 }
815
msm_chg_check_secondary_det(struct msm_otg * motg)816 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
817 {
818 struct usb_phy *phy = &motg->phy;
819 u32 chg_det;
820 bool ret = false;
821
822 switch (motg->pdata->phy_type) {
823 case CI_45NM_INTEGRATED_PHY:
824 chg_det = ulpi_read(phy, 0x34);
825 ret = chg_det & (1 << 4);
826 break;
827 case SNPS_28NM_INTEGRATED_PHY:
828 chg_det = ulpi_read(phy, 0x87);
829 ret = chg_det & 1;
830 break;
831 default:
832 break;
833 }
834 return ret;
835 }
836
msm_chg_enable_secondary_det(struct msm_otg * motg)837 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
838 {
839 struct usb_phy *phy = &motg->phy;
840 u32 chg_det;
841
842 switch (motg->pdata->phy_type) {
843 case CI_45NM_INTEGRATED_PHY:
844 chg_det = ulpi_read(phy, 0x34);
845 /* Turn off charger block */
846 chg_det |= ~(1 << 1);
847 ulpi_write(phy, chg_det, 0x34);
848 udelay(20);
849 /* control chg block via ULPI */
850 chg_det &= ~(1 << 3);
851 ulpi_write(phy, chg_det, 0x34);
852 /* put it in host mode for enabling D- source */
853 chg_det &= ~(1 << 2);
854 ulpi_write(phy, chg_det, 0x34);
855 /* Turn on chg detect block */
856 chg_det &= ~(1 << 1);
857 ulpi_write(phy, chg_det, 0x34);
858 udelay(20);
859 /* enable chg detection */
860 chg_det &= ~(1 << 0);
861 ulpi_write(phy, chg_det, 0x34);
862 break;
863 case SNPS_28NM_INTEGRATED_PHY:
864 /*
865 * Configure DM as current source, DP as current sink
866 * and enable battery charging comparators.
867 */
868 ulpi_write(phy, 0x8, 0x85);
869 ulpi_write(phy, 0x2, 0x85);
870 ulpi_write(phy, 0x1, 0x85);
871 break;
872 default:
873 break;
874 }
875 }
876
msm_chg_check_primary_det(struct msm_otg * motg)877 static bool msm_chg_check_primary_det(struct msm_otg *motg)
878 {
879 struct usb_phy *phy = &motg->phy;
880 u32 chg_det;
881 bool ret = false;
882
883 switch (motg->pdata->phy_type) {
884 case CI_45NM_INTEGRATED_PHY:
885 chg_det = ulpi_read(phy, 0x34);
886 ret = chg_det & (1 << 4);
887 break;
888 case SNPS_28NM_INTEGRATED_PHY:
889 chg_det = ulpi_read(phy, 0x87);
890 ret = chg_det & 1;
891 break;
892 default:
893 break;
894 }
895 return ret;
896 }
897
msm_chg_enable_primary_det(struct msm_otg * motg)898 static void msm_chg_enable_primary_det(struct msm_otg *motg)
899 {
900 struct usb_phy *phy = &motg->phy;
901 u32 chg_det;
902
903 switch (motg->pdata->phy_type) {
904 case CI_45NM_INTEGRATED_PHY:
905 chg_det = ulpi_read(phy, 0x34);
906 /* enable chg detection */
907 chg_det &= ~(1 << 0);
908 ulpi_write(phy, chg_det, 0x34);
909 break;
910 case SNPS_28NM_INTEGRATED_PHY:
911 /*
912 * Configure DP as current source, DM as current sink
913 * and enable battery charging comparators.
914 */
915 ulpi_write(phy, 0x2, 0x85);
916 ulpi_write(phy, 0x1, 0x85);
917 break;
918 default:
919 break;
920 }
921 }
922
msm_chg_check_dcd(struct msm_otg * motg)923 static bool msm_chg_check_dcd(struct msm_otg *motg)
924 {
925 struct usb_phy *phy = &motg->phy;
926 u32 line_state;
927 bool ret = false;
928
929 switch (motg->pdata->phy_type) {
930 case CI_45NM_INTEGRATED_PHY:
931 line_state = ulpi_read(phy, 0x15);
932 ret = !(line_state & 1);
933 break;
934 case SNPS_28NM_INTEGRATED_PHY:
935 line_state = ulpi_read(phy, 0x87);
936 ret = line_state & 2;
937 break;
938 default:
939 break;
940 }
941 return ret;
942 }
943
msm_chg_disable_dcd(struct msm_otg * motg)944 static void msm_chg_disable_dcd(struct msm_otg *motg)
945 {
946 struct usb_phy *phy = &motg->phy;
947 u32 chg_det;
948
949 switch (motg->pdata->phy_type) {
950 case CI_45NM_INTEGRATED_PHY:
951 chg_det = ulpi_read(phy, 0x34);
952 chg_det &= ~(1 << 5);
953 ulpi_write(phy, chg_det, 0x34);
954 break;
955 case SNPS_28NM_INTEGRATED_PHY:
956 ulpi_write(phy, 0x10, 0x86);
957 break;
958 default:
959 break;
960 }
961 }
962
msm_chg_enable_dcd(struct msm_otg * motg)963 static void msm_chg_enable_dcd(struct msm_otg *motg)
964 {
965 struct usb_phy *phy = &motg->phy;
966 u32 chg_det;
967
968 switch (motg->pdata->phy_type) {
969 case CI_45NM_INTEGRATED_PHY:
970 chg_det = ulpi_read(phy, 0x34);
971 /* Turn on D+ current source */
972 chg_det |= (1 << 5);
973 ulpi_write(phy, chg_det, 0x34);
974 break;
975 case SNPS_28NM_INTEGRATED_PHY:
976 /* Data contact detection enable */
977 ulpi_write(phy, 0x10, 0x85);
978 break;
979 default:
980 break;
981 }
982 }
983
msm_chg_block_on(struct msm_otg * motg)984 static void msm_chg_block_on(struct msm_otg *motg)
985 {
986 struct usb_phy *phy = &motg->phy;
987 u32 func_ctrl, chg_det;
988
989 /* put the controller in non-driving mode */
990 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
991 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
992 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
993 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
994
995 switch (motg->pdata->phy_type) {
996 case CI_45NM_INTEGRATED_PHY:
997 chg_det = ulpi_read(phy, 0x34);
998 /* control chg block via ULPI */
999 chg_det &= ~(1 << 3);
1000 ulpi_write(phy, chg_det, 0x34);
1001 /* Turn on chg detect block */
1002 chg_det &= ~(1 << 1);
1003 ulpi_write(phy, chg_det, 0x34);
1004 udelay(20);
1005 break;
1006 case SNPS_28NM_INTEGRATED_PHY:
1007 /* Clear charger detecting control bits */
1008 ulpi_write(phy, 0x3F, 0x86);
1009 /* Clear alt interrupt latch and enable bits */
1010 ulpi_write(phy, 0x1F, 0x92);
1011 ulpi_write(phy, 0x1F, 0x95);
1012 udelay(100);
1013 break;
1014 default:
1015 break;
1016 }
1017 }
1018
msm_chg_block_off(struct msm_otg * motg)1019 static void msm_chg_block_off(struct msm_otg *motg)
1020 {
1021 struct usb_phy *phy = &motg->phy;
1022 u32 func_ctrl, chg_det;
1023
1024 switch (motg->pdata->phy_type) {
1025 case CI_45NM_INTEGRATED_PHY:
1026 chg_det = ulpi_read(phy, 0x34);
1027 /* Turn off charger block */
1028 chg_det |= ~(1 << 1);
1029 ulpi_write(phy, chg_det, 0x34);
1030 break;
1031 case SNPS_28NM_INTEGRATED_PHY:
1032 /* Clear charger detecting control bits */
1033 ulpi_write(phy, 0x3F, 0x86);
1034 /* Clear alt interrupt latch and enable bits */
1035 ulpi_write(phy, 0x1F, 0x92);
1036 ulpi_write(phy, 0x1F, 0x95);
1037 break;
1038 default:
1039 break;
1040 }
1041
1042 /* put the controller in normal mode */
1043 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1044 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1045 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1046 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1047 }
1048
1049 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1050 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1051 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1052 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
msm_chg_detect_work(struct work_struct * w)1053 static void msm_chg_detect_work(struct work_struct *w)
1054 {
1055 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1056 struct usb_phy *phy = &motg->phy;
1057 bool is_dcd, tmout, vout;
1058 unsigned long delay;
1059
1060 dev_dbg(phy->dev, "chg detection work\n");
1061 switch (motg->chg_state) {
1062 case USB_CHG_STATE_UNDEFINED:
1063 pm_runtime_get_sync(phy->dev);
1064 msm_chg_block_on(motg);
1065 msm_chg_enable_dcd(motg);
1066 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1067 motg->dcd_retries = 0;
1068 delay = MSM_CHG_DCD_POLL_TIME;
1069 break;
1070 case USB_CHG_STATE_WAIT_FOR_DCD:
1071 is_dcd = msm_chg_check_dcd(motg);
1072 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1073 if (is_dcd || tmout) {
1074 msm_chg_disable_dcd(motg);
1075 msm_chg_enable_primary_det(motg);
1076 delay = MSM_CHG_PRIMARY_DET_TIME;
1077 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1078 } else {
1079 delay = MSM_CHG_DCD_POLL_TIME;
1080 }
1081 break;
1082 case USB_CHG_STATE_DCD_DONE:
1083 vout = msm_chg_check_primary_det(motg);
1084 if (vout) {
1085 msm_chg_enable_secondary_det(motg);
1086 delay = MSM_CHG_SECONDARY_DET_TIME;
1087 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1088 } else {
1089 motg->chg_type = USB_SDP_CHARGER;
1090 motg->chg_state = USB_CHG_STATE_DETECTED;
1091 delay = 0;
1092 }
1093 break;
1094 case USB_CHG_STATE_PRIMARY_DONE:
1095 vout = msm_chg_check_secondary_det(motg);
1096 if (vout)
1097 motg->chg_type = USB_DCP_CHARGER;
1098 else
1099 motg->chg_type = USB_CDP_CHARGER;
1100 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1101 /* fall through */
1102 case USB_CHG_STATE_SECONDARY_DONE:
1103 motg->chg_state = USB_CHG_STATE_DETECTED;
1104 case USB_CHG_STATE_DETECTED:
1105 msm_chg_block_off(motg);
1106 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1107 schedule_work(&motg->sm_work);
1108 return;
1109 default:
1110 return;
1111 }
1112
1113 schedule_delayed_work(&motg->chg_work, delay);
1114 }
1115
1116 /*
1117 * We support OTG, Peripheral only and Host only configurations. In case
1118 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1119 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1120 * enabled when switch is controlled by user and default mode is supplied
1121 * by board file, which can be changed by userspace later.
1122 */
msm_otg_init_sm(struct msm_otg * motg)1123 static void msm_otg_init_sm(struct msm_otg *motg)
1124 {
1125 struct msm_otg_platform_data *pdata = motg->pdata;
1126 u32 otgsc = readl(USB_OTGSC);
1127
1128 switch (pdata->mode) {
1129 case USB_DR_MODE_OTG:
1130 if (pdata->otg_control == OTG_PHY_CONTROL) {
1131 if (otgsc & OTGSC_ID)
1132 set_bit(ID, &motg->inputs);
1133 else
1134 clear_bit(ID, &motg->inputs);
1135
1136 if (otgsc & OTGSC_BSV)
1137 set_bit(B_SESS_VLD, &motg->inputs);
1138 else
1139 clear_bit(B_SESS_VLD, &motg->inputs);
1140 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1141 set_bit(ID, &motg->inputs);
1142 clear_bit(B_SESS_VLD, &motg->inputs);
1143 }
1144 break;
1145 case USB_DR_MODE_HOST:
1146 clear_bit(ID, &motg->inputs);
1147 break;
1148 case USB_DR_MODE_PERIPHERAL:
1149 set_bit(ID, &motg->inputs);
1150 if (otgsc & OTGSC_BSV)
1151 set_bit(B_SESS_VLD, &motg->inputs);
1152 else
1153 clear_bit(B_SESS_VLD, &motg->inputs);
1154 break;
1155 default:
1156 break;
1157 }
1158 }
1159
msm_otg_sm_work(struct work_struct * w)1160 static void msm_otg_sm_work(struct work_struct *w)
1161 {
1162 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1163 struct usb_otg *otg = motg->phy.otg;
1164
1165 switch (otg->state) {
1166 case OTG_STATE_UNDEFINED:
1167 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1168 msm_otg_reset(otg->usb_phy);
1169 msm_otg_init_sm(motg);
1170 otg->state = OTG_STATE_B_IDLE;
1171 /* FALL THROUGH */
1172 case OTG_STATE_B_IDLE:
1173 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1174 if (!test_bit(ID, &motg->inputs) && otg->host) {
1175 /* disable BSV bit */
1176 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1177 msm_otg_start_host(otg->usb_phy, 1);
1178 otg->state = OTG_STATE_A_HOST;
1179 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1180 switch (motg->chg_state) {
1181 case USB_CHG_STATE_UNDEFINED:
1182 msm_chg_detect_work(&motg->chg_work.work);
1183 break;
1184 case USB_CHG_STATE_DETECTED:
1185 switch (motg->chg_type) {
1186 case USB_DCP_CHARGER:
1187 msm_otg_notify_charger(motg,
1188 IDEV_CHG_MAX);
1189 break;
1190 case USB_CDP_CHARGER:
1191 msm_otg_notify_charger(motg,
1192 IDEV_CHG_MAX);
1193 msm_otg_start_peripheral(otg->usb_phy,
1194 1);
1195 otg->state
1196 = OTG_STATE_B_PERIPHERAL;
1197 break;
1198 case USB_SDP_CHARGER:
1199 msm_otg_notify_charger(motg, IUNIT);
1200 msm_otg_start_peripheral(otg->usb_phy,
1201 1);
1202 otg->state
1203 = OTG_STATE_B_PERIPHERAL;
1204 break;
1205 default:
1206 break;
1207 }
1208 break;
1209 default:
1210 break;
1211 }
1212 } else {
1213 /*
1214 * If charger detection work is pending, decrement
1215 * the pm usage counter to balance with the one that
1216 * is incremented in charger detection work.
1217 */
1218 if (cancel_delayed_work_sync(&motg->chg_work)) {
1219 pm_runtime_put_sync(otg->usb_phy->dev);
1220 msm_otg_reset(otg->usb_phy);
1221 }
1222 msm_otg_notify_charger(motg, 0);
1223 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1224 motg->chg_type = USB_INVALID_CHARGER;
1225 }
1226
1227 if (otg->state == OTG_STATE_B_IDLE)
1228 pm_runtime_put_sync(otg->usb_phy->dev);
1229 break;
1230 case OTG_STATE_B_PERIPHERAL:
1231 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1232 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1233 !test_bit(ID, &motg->inputs)) {
1234 msm_otg_notify_charger(motg, 0);
1235 msm_otg_start_peripheral(otg->usb_phy, 0);
1236 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1237 motg->chg_type = USB_INVALID_CHARGER;
1238 otg->state = OTG_STATE_B_IDLE;
1239 msm_otg_reset(otg->usb_phy);
1240 schedule_work(w);
1241 }
1242 break;
1243 case OTG_STATE_A_HOST:
1244 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1245 if (test_bit(ID, &motg->inputs)) {
1246 msm_otg_start_host(otg->usb_phy, 0);
1247 otg->state = OTG_STATE_B_IDLE;
1248 msm_otg_reset(otg->usb_phy);
1249 schedule_work(w);
1250 }
1251 break;
1252 default:
1253 break;
1254 }
1255 }
1256
msm_otg_irq(int irq,void * data)1257 static irqreturn_t msm_otg_irq(int irq, void *data)
1258 {
1259 struct msm_otg *motg = data;
1260 struct usb_phy *phy = &motg->phy;
1261 u32 otgsc = 0;
1262
1263 if (atomic_read(&motg->in_lpm)) {
1264 disable_irq_nosync(irq);
1265 motg->async_int = 1;
1266 pm_runtime_get(phy->dev);
1267 return IRQ_HANDLED;
1268 }
1269
1270 otgsc = readl(USB_OTGSC);
1271 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1272 return IRQ_NONE;
1273
1274 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1275 if (otgsc & OTGSC_ID)
1276 set_bit(ID, &motg->inputs);
1277 else
1278 clear_bit(ID, &motg->inputs);
1279 dev_dbg(phy->dev, "ID set/clear\n");
1280 pm_runtime_get_noresume(phy->dev);
1281 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1282 if (otgsc & OTGSC_BSV)
1283 set_bit(B_SESS_VLD, &motg->inputs);
1284 else
1285 clear_bit(B_SESS_VLD, &motg->inputs);
1286 dev_dbg(phy->dev, "BSV set/clear\n");
1287 pm_runtime_get_noresume(phy->dev);
1288 }
1289
1290 writel(otgsc, USB_OTGSC);
1291 schedule_work(&motg->sm_work);
1292 return IRQ_HANDLED;
1293 }
1294
msm_otg_mode_show(struct seq_file * s,void * unused)1295 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1296 {
1297 struct msm_otg *motg = s->private;
1298 struct usb_otg *otg = motg->phy.otg;
1299
1300 switch (otg->state) {
1301 case OTG_STATE_A_HOST:
1302 seq_puts(s, "host\n");
1303 break;
1304 case OTG_STATE_B_PERIPHERAL:
1305 seq_puts(s, "peripheral\n");
1306 break;
1307 default:
1308 seq_puts(s, "none\n");
1309 break;
1310 }
1311
1312 return 0;
1313 }
1314
msm_otg_mode_open(struct inode * inode,struct file * file)1315 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1316 {
1317 return single_open(file, msm_otg_mode_show, inode->i_private);
1318 }
1319
msm_otg_mode_write(struct file * file,const char __user * ubuf,size_t count,loff_t * ppos)1320 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1321 size_t count, loff_t *ppos)
1322 {
1323 struct seq_file *s = file->private_data;
1324 struct msm_otg *motg = s->private;
1325 char buf[16];
1326 struct usb_otg *otg = motg->phy.otg;
1327 int status = count;
1328 enum usb_dr_mode req_mode;
1329
1330 memset(buf, 0x00, sizeof(buf));
1331
1332 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1333 status = -EFAULT;
1334 goto out;
1335 }
1336
1337 if (!strncmp(buf, "host", 4)) {
1338 req_mode = USB_DR_MODE_HOST;
1339 } else if (!strncmp(buf, "peripheral", 10)) {
1340 req_mode = USB_DR_MODE_PERIPHERAL;
1341 } else if (!strncmp(buf, "none", 4)) {
1342 req_mode = USB_DR_MODE_UNKNOWN;
1343 } else {
1344 status = -EINVAL;
1345 goto out;
1346 }
1347
1348 switch (req_mode) {
1349 case USB_DR_MODE_UNKNOWN:
1350 switch (otg->state) {
1351 case OTG_STATE_A_HOST:
1352 case OTG_STATE_B_PERIPHERAL:
1353 set_bit(ID, &motg->inputs);
1354 clear_bit(B_SESS_VLD, &motg->inputs);
1355 break;
1356 default:
1357 goto out;
1358 }
1359 break;
1360 case USB_DR_MODE_PERIPHERAL:
1361 switch (otg->state) {
1362 case OTG_STATE_B_IDLE:
1363 case OTG_STATE_A_HOST:
1364 set_bit(ID, &motg->inputs);
1365 set_bit(B_SESS_VLD, &motg->inputs);
1366 break;
1367 default:
1368 goto out;
1369 }
1370 break;
1371 case USB_DR_MODE_HOST:
1372 switch (otg->state) {
1373 case OTG_STATE_B_IDLE:
1374 case OTG_STATE_B_PERIPHERAL:
1375 clear_bit(ID, &motg->inputs);
1376 break;
1377 default:
1378 goto out;
1379 }
1380 break;
1381 default:
1382 goto out;
1383 }
1384
1385 pm_runtime_get_sync(otg->usb_phy->dev);
1386 schedule_work(&motg->sm_work);
1387 out:
1388 return status;
1389 }
1390
1391 static const struct file_operations msm_otg_mode_fops = {
1392 .open = msm_otg_mode_open,
1393 .read = seq_read,
1394 .write = msm_otg_mode_write,
1395 .llseek = seq_lseek,
1396 .release = single_release,
1397 };
1398
1399 static struct dentry *msm_otg_dbg_root;
1400 static struct dentry *msm_otg_dbg_mode;
1401
msm_otg_debugfs_init(struct msm_otg * motg)1402 static int msm_otg_debugfs_init(struct msm_otg *motg)
1403 {
1404 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1405
1406 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1407 return -ENODEV;
1408
1409 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1410 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1411 if (!msm_otg_dbg_mode) {
1412 debugfs_remove(msm_otg_dbg_root);
1413 msm_otg_dbg_root = NULL;
1414 return -ENODEV;
1415 }
1416
1417 return 0;
1418 }
1419
msm_otg_debugfs_cleanup(void)1420 static void msm_otg_debugfs_cleanup(void)
1421 {
1422 debugfs_remove(msm_otg_dbg_mode);
1423 debugfs_remove(msm_otg_dbg_root);
1424 }
1425
1426 static const struct of_device_id msm_otg_dt_match[] = {
1427 {
1428 .compatible = "qcom,usb-otg-ci",
1429 .data = (void *) CI_45NM_INTEGRATED_PHY
1430 },
1431 {
1432 .compatible = "qcom,usb-otg-snps",
1433 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1434 },
1435 { }
1436 };
1437 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1438
msm_otg_read_dt(struct platform_device * pdev,struct msm_otg * motg)1439 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1440 {
1441 struct msm_otg_platform_data *pdata;
1442 const struct of_device_id *id;
1443 struct device_node *node = pdev->dev.of_node;
1444 struct property *prop;
1445 int len, ret, words;
1446 u32 val, tmp[3];
1447
1448 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1449 if (!pdata)
1450 return -ENOMEM;
1451
1452 motg->pdata = pdata;
1453
1454 id = of_match_device(msm_otg_dt_match, &pdev->dev);
1455 pdata->phy_type = (enum msm_usb_phy_type) id->data;
1456
1457 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1458 if (IS_ERR(motg->link_rst))
1459 return PTR_ERR(motg->link_rst);
1460
1461 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1462 if (IS_ERR(motg->phy_rst))
1463 motg->phy_rst = NULL;
1464
1465 pdata->mode = of_usb_get_dr_mode(node);
1466 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1467 pdata->mode = USB_DR_MODE_OTG;
1468
1469 pdata->otg_control = OTG_PHY_CONTROL;
1470 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1471 if (val == OTG_PMIC_CONTROL)
1472 pdata->otg_control = val;
1473
1474 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1475 motg->phy_number = val;
1476
1477 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1478 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1479 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1480
1481 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1482 len == sizeof(tmp)) {
1483 of_property_read_u32_array(node, "qcom,vdd-levels",
1484 tmp, len / sizeof(*tmp));
1485 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1486 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1487 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1488 }
1489
1490 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1491 if (!prop || !len)
1492 return 0;
1493
1494 words = len / sizeof(u32);
1495
1496 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1497 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1498 return 0;
1499 }
1500
1501 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1502 if (!pdata->phy_init_seq)
1503 return 0;
1504
1505 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1506 pdata->phy_init_seq, words);
1507 if (!ret)
1508 pdata->phy_init_sz = words;
1509
1510 return 0;
1511 }
1512
msm_otg_probe(struct platform_device * pdev)1513 static int msm_otg_probe(struct platform_device *pdev)
1514 {
1515 struct regulator_bulk_data regs[3];
1516 int ret = 0;
1517 struct device_node *np = pdev->dev.of_node;
1518 struct msm_otg_platform_data *pdata;
1519 struct resource *res;
1520 struct msm_otg *motg;
1521 struct usb_phy *phy;
1522 void __iomem *phy_select;
1523
1524 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1525 if (!motg)
1526 return -ENOMEM;
1527
1528 pdata = dev_get_platdata(&pdev->dev);
1529 if (!pdata) {
1530 if (!np)
1531 return -ENXIO;
1532 ret = msm_otg_read_dt(pdev, motg);
1533 if (ret)
1534 return ret;
1535 }
1536
1537 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1538 GFP_KERNEL);
1539 if (!motg->phy.otg)
1540 return -ENOMEM;
1541
1542 phy = &motg->phy;
1543 phy->dev = &pdev->dev;
1544
1545 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1546 if (IS_ERR(motg->clk)) {
1547 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1548 return PTR_ERR(motg->clk);
1549 }
1550
1551 /*
1552 * If USB Core is running its protocol engine based on CORE CLK,
1553 * CORE CLK must be running at >55Mhz for correct HSUSB
1554 * operation and USB core cannot tolerate frequency changes on
1555 * CORE CLK.
1556 */
1557 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1558 if (IS_ERR(motg->pclk)) {
1559 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1560 return PTR_ERR(motg->pclk);
1561 }
1562
1563 /*
1564 * USB core clock is not present on all MSM chips. This
1565 * clock is introduced to remove the dependency on AXI
1566 * bus frequency.
1567 */
1568 motg->core_clk = devm_clk_get(&pdev->dev,
1569 np ? "alt_core" : "usb_hs_core_clk");
1570
1571 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1572 if (!res)
1573 return -EINVAL;
1574 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1575 if (!motg->regs)
1576 return -ENOMEM;
1577
1578 /*
1579 * NOTE: The PHYs can be multiplexed between the chipidea controller
1580 * and the dwc3 controller, using a single bit. It is important that
1581 * the dwc3 driver does not set this bit in an incompatible way.
1582 */
1583 if (motg->phy_number) {
1584 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1585 if (!phy_select)
1586 return -ENOMEM;
1587 /* Enable second PHY with the OTG port */
1588 writel(0x1, phy_select);
1589 }
1590
1591 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1592
1593 motg->irq = platform_get_irq(pdev, 0);
1594 if (motg->irq < 0) {
1595 dev_err(&pdev->dev, "platform_get_irq failed\n");
1596 return motg->irq;
1597 }
1598
1599 regs[0].supply = "vddcx";
1600 regs[1].supply = "v3p3";
1601 regs[2].supply = "v1p8";
1602
1603 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1604 if (ret)
1605 return ret;
1606
1607 motg->vddcx = regs[0].consumer;
1608 motg->v3p3 = regs[1].consumer;
1609 motg->v1p8 = regs[2].consumer;
1610
1611 clk_set_rate(motg->clk, 60000000);
1612
1613 clk_prepare_enable(motg->clk);
1614 clk_prepare_enable(motg->pclk);
1615
1616 if (!IS_ERR(motg->core_clk))
1617 clk_prepare_enable(motg->core_clk);
1618
1619 ret = msm_hsusb_init_vddcx(motg, 1);
1620 if (ret) {
1621 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1622 goto disable_clks;
1623 }
1624
1625 ret = msm_hsusb_ldo_init(motg, 1);
1626 if (ret) {
1627 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1628 goto disable_vddcx;
1629 }
1630 ret = msm_hsusb_ldo_set_mode(motg, 1);
1631 if (ret) {
1632 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1633 goto disable_ldo;
1634 }
1635
1636 writel(0, USB_USBINTR);
1637 writel(0, USB_OTGSC);
1638
1639 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1640 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1641 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1642 "msm_otg", motg);
1643 if (ret) {
1644 dev_err(&pdev->dev, "request irq failed\n");
1645 goto disable_ldo;
1646 }
1647
1648 phy->init = msm_phy_init;
1649 phy->set_power = msm_otg_set_power;
1650 phy->notify_disconnect = msm_phy_notify_disconnect;
1651 phy->type = USB_PHY_TYPE_USB2;
1652
1653 phy->io_ops = &msm_otg_io_ops;
1654
1655 phy->otg->usb_phy = &motg->phy;
1656 phy->otg->set_host = msm_otg_set_host;
1657 phy->otg->set_peripheral = msm_otg_set_peripheral;
1658
1659 msm_usb_reset(phy);
1660
1661 ret = usb_add_phy_dev(&motg->phy);
1662 if (ret) {
1663 dev_err(&pdev->dev, "usb_add_phy failed\n");
1664 goto disable_ldo;
1665 }
1666
1667 platform_set_drvdata(pdev, motg);
1668 device_init_wakeup(&pdev->dev, 1);
1669
1670 if (motg->pdata->mode == USB_DR_MODE_OTG &&
1671 motg->pdata->otg_control == OTG_USER_CONTROL) {
1672 ret = msm_otg_debugfs_init(motg);
1673 if (ret)
1674 dev_dbg(&pdev->dev, "Can not create mode change file\n");
1675 }
1676
1677 pm_runtime_set_active(&pdev->dev);
1678 pm_runtime_enable(&pdev->dev);
1679
1680 return 0;
1681
1682 disable_ldo:
1683 msm_hsusb_ldo_init(motg, 0);
1684 disable_vddcx:
1685 msm_hsusb_init_vddcx(motg, 0);
1686 disable_clks:
1687 clk_disable_unprepare(motg->pclk);
1688 clk_disable_unprepare(motg->clk);
1689 if (!IS_ERR(motg->core_clk))
1690 clk_disable_unprepare(motg->core_clk);
1691 return ret;
1692 }
1693
msm_otg_remove(struct platform_device * pdev)1694 static int msm_otg_remove(struct platform_device *pdev)
1695 {
1696 struct msm_otg *motg = platform_get_drvdata(pdev);
1697 struct usb_phy *phy = &motg->phy;
1698 int cnt = 0;
1699
1700 if (phy->otg->host || phy->otg->gadget)
1701 return -EBUSY;
1702
1703 msm_otg_debugfs_cleanup();
1704 cancel_delayed_work_sync(&motg->chg_work);
1705 cancel_work_sync(&motg->sm_work);
1706
1707 pm_runtime_resume(&pdev->dev);
1708
1709 device_init_wakeup(&pdev->dev, 0);
1710 pm_runtime_disable(&pdev->dev);
1711
1712 usb_remove_phy(phy);
1713 disable_irq(motg->irq);
1714
1715 /*
1716 * Put PHY in low power mode.
1717 */
1718 ulpi_read(phy, 0x14);
1719 ulpi_write(phy, 0x08, 0x09);
1720
1721 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1722 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1723 if (readl(USB_PORTSC) & PORTSC_PHCD)
1724 break;
1725 udelay(1);
1726 cnt++;
1727 }
1728 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1729 dev_err(phy->dev, "Unable to suspend PHY\n");
1730
1731 clk_disable_unprepare(motg->pclk);
1732 clk_disable_unprepare(motg->clk);
1733 if (!IS_ERR(motg->core_clk))
1734 clk_disable_unprepare(motg->core_clk);
1735 msm_hsusb_ldo_init(motg, 0);
1736
1737 pm_runtime_set_suspended(&pdev->dev);
1738
1739 return 0;
1740 }
1741
1742 #ifdef CONFIG_PM
msm_otg_runtime_idle(struct device * dev)1743 static int msm_otg_runtime_idle(struct device *dev)
1744 {
1745 struct msm_otg *motg = dev_get_drvdata(dev);
1746 struct usb_otg *otg = motg->phy.otg;
1747
1748 dev_dbg(dev, "OTG runtime idle\n");
1749
1750 /*
1751 * It is observed some times that a spurious interrupt
1752 * comes when PHY is put into LPM immediately after PHY reset.
1753 * This 1 sec delay also prevents entering into LPM immediately
1754 * after asynchronous interrupt.
1755 */
1756 if (otg->state != OTG_STATE_UNDEFINED)
1757 pm_schedule_suspend(dev, 1000);
1758
1759 return -EAGAIN;
1760 }
1761
msm_otg_runtime_suspend(struct device * dev)1762 static int msm_otg_runtime_suspend(struct device *dev)
1763 {
1764 struct msm_otg *motg = dev_get_drvdata(dev);
1765
1766 dev_dbg(dev, "OTG runtime suspend\n");
1767 return msm_otg_suspend(motg);
1768 }
1769
msm_otg_runtime_resume(struct device * dev)1770 static int msm_otg_runtime_resume(struct device *dev)
1771 {
1772 struct msm_otg *motg = dev_get_drvdata(dev);
1773
1774 dev_dbg(dev, "OTG runtime resume\n");
1775 return msm_otg_resume(motg);
1776 }
1777 #endif
1778
1779 #ifdef CONFIG_PM_SLEEP
msm_otg_pm_suspend(struct device * dev)1780 static int msm_otg_pm_suspend(struct device *dev)
1781 {
1782 struct msm_otg *motg = dev_get_drvdata(dev);
1783
1784 dev_dbg(dev, "OTG PM suspend\n");
1785 return msm_otg_suspend(motg);
1786 }
1787
msm_otg_pm_resume(struct device * dev)1788 static int msm_otg_pm_resume(struct device *dev)
1789 {
1790 struct msm_otg *motg = dev_get_drvdata(dev);
1791 int ret;
1792
1793 dev_dbg(dev, "OTG PM resume\n");
1794
1795 ret = msm_otg_resume(motg);
1796 if (ret)
1797 return ret;
1798
1799 /*
1800 * Runtime PM Documentation recommends bringing the
1801 * device to full powered state upon resume.
1802 */
1803 pm_runtime_disable(dev);
1804 pm_runtime_set_active(dev);
1805 pm_runtime_enable(dev);
1806
1807 return 0;
1808 }
1809 #endif
1810
1811 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1812 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1813 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1814 msm_otg_runtime_idle)
1815 };
1816
1817 static struct platform_driver msm_otg_driver = {
1818 .probe = msm_otg_probe,
1819 .remove = msm_otg_remove,
1820 .driver = {
1821 .name = DRIVER_NAME,
1822 .pm = &msm_otg_dev_pm_ops,
1823 .of_match_table = msm_otg_dt_match,
1824 },
1825 };
1826
1827 module_platform_driver(msm_otg_driver);
1828
1829 MODULE_LICENSE("GPL v2");
1830 MODULE_DESCRIPTION("MSM USB transceiver driver");
1831